Freescale Semiconductor MCF5480 - Manual (Page 387)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 15-15
Most PPDSDR_x registers have a full 8-bit implementation, as shown in Figure 15-12 . The remaining
PPDSDR_x registers use fewer than eight bits. Their bit definitions are shown in Figure 15-13 ,
Figure 15-14 , Figure 15-15 , and Figure 15-16 .
The PPDSDR_x registers are read/write. At reset, the bits in the PPDSDR_x registers are set to the current
pin states. Reading a PPDSDR_x register returns the current state of the port x pins. Writing 1s to a
PPDSDR_x register sets the corresponding bits in the PODR_x register. Writing 0s has no effect.
15.3.2.3.1 8-Bit PPDSDR_x Registers
The 8-bit PPDSDR_x registers include the following:
• PPDSDR_FBCTL
• PPDSDR_FEC0H
• PPDSDR_FEC0L
• PPDSDR_FEC1H
• PPDSDR_FEC1L
• PPDSDR_PSC3PSC2
• PPDSDR_PSC1PSC0
• PPDSDR_PSC3PSC2
Figure 15-12 displays the 8-bit PPDSDR_x registers.
15.3.2.3.2 7-Bit PPDSDR_x Register
The 7-bit PPDSDR_x register is for pin data and set data for PDSPIn. Figure 15-13 displays the 7-bit
PPDSDR_DSPI register.
7 6 5 4 3 2 1 0
R PPDx7 PPDx6 PPDx5 PPDx4 PPDx3 PPDx2 PPDx1 PPDx0
W PSDx7 PSDx6 PSDx5 PSDx4 PSDx3 PSDx2 PSDx1 PSDx0
Reset P
1
P
1
P
1
P
1
P
1
P
1
P
1
P
1
Reg
Addr
MBAR + 0xA20 (PPDSDR_FBCTL), 0xA24 (PPDSDR_FEC0H), 0xA25 (PPDSDR_FEC0L), 0xA26
(PPDSDR_FEC1H), 0xA27 (PPDSDR_FEC1L), 0xA2C (PPDSDR_PSC3PSC2), 0xA2D (PPDSDR_PSC1PSC0)
1
P = the current pin state. The exception is that PPDSDR_FBCTL is always reset to 0.
Figure 15-12. 8-Bit Port Pin Data / Set Data Registers
Table 15-14. 8-Bit PPDSDR_x Field Descriptions
Bits Name Description
7–0 PPDxn Port pin data. This is read-only.
0 Port x pin state is low
1 Port x pin state is high
PSDxn Port set data.
0 No effect
1 Corresponding PODR_x bit is set