4 4-bit ppdsdr_x registers, 5 fbcs register (ppdsdr_fbcs), Figure 15-15 – Freescale Semiconductor MCF5480 User Manual
Page 389

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
15-17
15.3.2.3.4
4-Bit PPDSDR_x Registers
The 4-bit PPDSDR_x registers are the pin data and set data registers for PDMAn (PPDSDR_DMA) and
PFECI2Cn (PPDSDR_FECI2C).
displays the 4-bit PPDSDR_DMA and PPDSDR_FECI2C
registers.
15.3.2.3.5
FBCS Register (PPDSDR_FBCS)
The 5-bit PPDSDR_FBCS register is for pin data and set data for PFBCSn.
PPDSDR_FBCS register.
4–0
PPDxn
PPDSDR_PCIBG and PPDSDR_PCIBR pin data. This is Read-only.
0 PPCIBGn or PPCIBRn pin state is low
1 PPCIBGn or PPCIBRn pin state is high
PSDxn
PPDSDR_PCIBG and PPDSDR_PCIBR set data.
0 No effect
1 Corresponding PODR_PCIBGn or PODR_PCIBRn bit is set
7
6
5
4
3
2
1
0
R
0
0
0
0
PPDx3
PPDx2
PPDx1
PPDx0
W
PSDx3
PSDx2
PSDx1
PSDx0
Reset
0
0
0
0
P
1
P
1
P
1
P
1
Reg
Addr
MBAR + 0xA22 (PPDSDR_DMA) and 0xA28 (PPDSDR_FECI2C)
1
P = the current pin state.
Figure 15-15. 4-Bit PPDSDR_DMA and PPDSDR_FECI2C Registers
Table 15-17. 4-Bit PPDSDR_DMA and PPDSDR_FECI2C Field Descriptions
Bits
Name Description
7–4
—
Reserved, should be cleared.
4–0
PPDxn
PPDSDR_DMA and PPDSDR_FECI2C pin data. This is Read-only.
0 PDMAn or PFECI2Cn pin state is low
1 PDMAn or PFECI2Cn pin state is high
PSDXn
PPDSDR_DMA and PPDSDR_FECI2C set data.
0 No effect
1 Corresponding PODR_DMA or PODR_FECI2C bit is set
Table 15-16. 5-Bit PPDSDR_PCIBG and PPDSDR_PCIBR Field Descriptions (Continued)
Bits
Name Description