Freescale Semiconductor MCF5480 - Manual (Page 106)

MCF548x Reference Manual, Rev. 3
3-2 Freescale Semiconductor
3.2.1 Enhanced Pipelines
The IFP prefetches instructions. The OEP decodes instructions, fetches required operands, then executes
the specified function. The two independent, decoupled pipeline structures maximize performance while
minimizing core size. Pipeline stages are shown in Figure 3-1 and are summarized as follows:
• Four-stage IFP (plus optional instruction buffer stage)
— Instruction address generation (IAG) calculates the next prefetch address.
— Instruction fetch cycle 1 (IC1) initiates prefetch on the processor’s local instruction bus.
— Instruction fetch cycle 2 (IC2) completes prefetch on the processor’s local instruction bus.
— Instruction early decode (IED) generates time-critical decode signals needed for the OEP.
— Instruction buffer (IB) stage uses FIFO queue to minimize effects of fetch latency.
• Five-stage OEP with two optional processor bus write cycles
— Decode stage (DS/secDS) decodes and selects for two sequential instructions.
— Operand address generation (OAG) generates the address for the data operand.
— Operand fetch cycle 1 and 2 (OC1 and OC2) fetch data operands.
— Execute (EX) performs prescribed operations on previously fetched data operands.
— Write data available (DA) makes data available for operand write operations only.
— Store data (ST) updates memory element for operand write operations only.