Freescale Semiconductor MCF5480 - Manual (Page 17)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor xvii
Contents
Paragraph
Number
Title
Page
Number
Chapter 14
Edge Port Module (EPORT)
14.1 Introduction ................................................................................................................... 14-1
14.2 Interrupt/General-Purpose I/O Pin Descriptions ........................................................... 14-1
14.3 Memory Map/Register Definition ................................................................................ 14-2
14.3.1 Memory Map ............................................................................................................ 14-2
14.3.2 Register Descriptions ................................................................................................ 14-2
14.3.2.1 EPORT Pin Assignment Register (EPPAR) ......................................................... 14-3
14.3.2.2 EPORT Data Direction Register (EPDDR) .......................................................... 14-3
14.3.2.3 Edge Port Interrupt Enable Register (EPIER) ...................................................... 14-4
14.3.2.4 Edge Port Data Register (EPDR) .......................................................................... 14-4
14.3.2.5 Edge Port Pin Data Register (EPPDR) ................................................................. 14-5
14.3.2.6 Edge Port Flag Register (EPFR) ........................................................................... 14-5
Chapter 15
GPIO
15.1 Introduction ................................................................................................................... 15-1
15.1.1 Overview ................................................................................................................... 15-2
15.1.2 Features ..................................................................................................................... 15-3
15.2 External Pin Description ............................................................................................... 15-3
15.3 Memory Map/Register Definition ................................................................................ 15-7
15.3.1 Register Overview .................................................................................................... 15-7
15.3.2 Register Descriptions ................................................................................................ 15-8
15.3.2.1 Port x Output Data Registers (PODR_x) .............................................................. 15-8
15.3.2.2 Port x Data Direction Registers (PDDR_x) ........................................................ 15-11
15.3.2.3 Port x Pin Data/Set Data Registers (PPDSDR_x) ............................................. 15-14
15.3.2.4 Port x Clear Output Data Registers (PCLRR_x) ................................................ 15-18
15.3.2.5 Port x Pin Assignment Registers (PAR_x) ......................................................... 15-21
15.3.2.6 FlexBus Chip Select Pin Assignment Register (PAR_FBCS) ........................... 15-22
15.3.2.7 DMA Pin Assignment Register (PAR_DMA) ................................................... 15-23
15.3.2.8 FEC/I2C/IRQ Pin Assignment Register (PAR_FECI2CIRQ) ........................... 15-23
15.3.2.9 PCI Grant Pin Assignment Register (PAR_PCIBG) .......................................... 15-25
15.3.2.10 PCI Request Pin Assignment Register (PAR_PCIBR) ...................................... 15-26
15.3.2.11 PSC3 Pin Assignment Register (PAR_PSC3) .................................................... 15-27
15.3.2.12 PSC2 Pin Assignment Register (PAR_PSC2) .................................................... 15-28
15.3.2.13 PSC1 Pin Assignment Register (PAR_PSC1) .................................................... 15-28
15.3.2.14 PSC0 Pin Assignment Register (PAR_PSC0) .................................................... 15-29
15.3.2.15 DSPI Pin Assignment Register (PAR_DSPI) ..................................................... 15-30
15.3.2.16 General Purpose Timer Pin Assignment Register (PAR_TIMER) .................... 15-31