Freescale Semiconductor MCF5480 - Manual (Page 933)

Introduction
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 30-3
30.1.4 Features
The FEC incorporates the following features:
• Support for three different Ethernet physical interfaces:
— 100-Mbps IEEE 802.3 MII
— 10-Mbps IEEE 802.3 MII
— 10-Mbps 7-wire interface
• IEEE 802.3 full duplex flow control
• Programmable max frame length supports IEEE 802.1 VLAN tags and priority
• Support for full-duplex operation (200Mbps throughput) with a minimum system clock rate of
50MHz
• Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of 25
MHz
• Retransmission from transmit FIFO following a collision (no processor bus utilization)
• Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
30.1.5 Modes of Operation
The primary operational modes are described in this section.
30.1.5.1 Full and Half Duplex Operation
Full duplex mode is intended for use on point to point links between switches or end node to switch. Half
duplex mode is used in connections between an end node and a repeater or between repeaters. Selection
of the duplex mode is controlled by TCR[FDEN] and RCR[DRT].
When configured for full duplex mode, flow control may be enabled. Refer to the TCR[RFC_PAUSE] and
TCR[TFC_PAUSE] bits, the RCR[FCE] bit, and Section 30.4.8, “Full Duplex Flow Control ,” for more
details.
30.1.5.2 Interface Options
The following interface options are supported. A detailed discussion of the interface configurations is
provided in Section 30.4.3, “Network Interface Options ”.
30.1.5.2.1 10 Mbps and 100 Mbps MII Interface
MII is the Media Independent Interface defined by the IEEE 802.3 standard for 10/100 Mbps operation.
The MAC-PHY interface may be configured to operate in MII mode by asserting RCR[MII_MODE].
The speed of operation is determined by the ETXCLK and ERXCLK signals which are driven by the
external transceiver. The transceiver will either auto-negotiate the speed or it may be controlled by
software via the serial management interface (EMDC/EMDIO signals) to the transceiver. Refer to the
MMFR and MSCR register descriptions as well as the description of how to read and write registers in the