6 mmu fault, test, or tlb address register (mmuar), Table 5-7, Describes mmusr fields – Freescale Semiconductor MCF5480 User Manual
Page 181
MMU Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
5-15
5.5.3.6
MMU Fault, Test, or TLB Address Register (MMUAR)
The MMUAR format,
, depends on how the register is used.
Table 5-7. MMUSR Field Descriptions
Bits
Name
Description
31–6
—
Reserved, should be cleared. Writes are ignored and reads return zeros.
5
SPF
Supervisor protect fault. Indicates if the last data fault was a user mode access that hit in
a TLB entry that had its supervisor protect bit set.
0 Last data access fault did not have a supervisor protect fault.
1 Last data access fault had a supervisor protect fault.
4
RF
Read access fault. Indicates if the last data fault was an data read access that hit in a TLB
entry that did not have its read bit set.
0 Last data access fault did not have a read protect fault.
1 Last data access fault had a read protect fault.
3
WF
Write access fault. Indicates if the last data fault was an data write access that hit in a TLB
entry that did not have its write bit set.
0 Last data access fault did not have a write protect fault.
1 Last data access fault had a write protect fault.
2
—
Reserved, should be cleared. Writes are ignored and reads return zeros.
1
HIT
Search TLB hit. Indicates if the last data fault or the last search TLB operation hit in the
TLB.
0 Last data access fault or search TLB operation did not hit in the TLB.
1 Last data access fault or search TLB operation hit in the TLB.
0
—
Reserved, should be cleared. Writes are ignored and reads return zeros.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
FA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
FA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MMUBAR + 0x010
Figure 5-7. MMU Fault, Test, or TLB Address Register (MMUAR)