4 aesu interrupt status register (aesisr), Aesu interrupt status register (aesisr) -53, P. 22-53 – Freescale Semiconductor MCF5480 User Manual
Page 655
Advanced Encryption Standard Execution Units (AESU)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
22-53
22.12.4 AESU Interrupt Status Register (AESISR)
The AESU interrupt status register tracks the state of possible errors, if those errors are not masked, via
the AESU interrupt mask register. The definition of each bit in the interrupt status register is shown in
.
Figure 22-38. AESU Interrupt Status Register (AESISR)
describes AESU interrupt register fields.
25
ID
Interrupt Done. This status bit reflects the state of the DONE interrupt signal, as sampled
by the controller interrupt status register (
Section 22.6.4.4, “SEC Interrupt Status Registers
”).
0 AESU is not signaling done
1 AESU is signaling done
24
RD
Reset Done. This status bit, when high, indicates that AESU has completed its reset
sequence, as reflected in the signal sampled by the appropriate crypto-channel.
0 Reset in progress
1 Reset done
23–0
—
Reserved
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
ME
AE
OFE
IFE
0
IFO
OFU
0
0
0
0
IE
ERE
CE
KSE
DSE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR 0x32030
Table 22-36. AESISR Field Descriptions
Bits
Name
Description
31
ME
Mode Error. Indicates that invalid data was written to a register or a reserved mode bit was
set.
0 Valid Data
1 Reserved or invalid mode selected
30
AE
Address Error. An illegal read or write address was detected within the AESU address
space.
0 No error detected
1 Address error
Table 22-35. AESSR Field Descriptions (Continued)
Bits
Name
Description