Freescale Semiconductor MCF5480 - Manual (Page 828)

MCF548x Reference Manual, Rev. 3
27-10 Freescale Semiconductor
7–4 DT Delay after transfer scaler. The DT field selects the delay after transfer scaler. This field is only used
in master mode. The delay after transfer is the time between the negation of the
DSPICS signal at
the end of a frame and the assertion of DSPICS at the beginning of the next frame. Table 27-7 lists
the scaler values.
The delay after transfer is a multiple of the system clock period and it is computed according to the
following equation:
Eqn. 27-3
See Section 27.7.3.4, “Delay after Transfer (tDT) ” for more details.
3–0 BR Baud rate scaler. The BR field selects the scaler value for the baud rate. This field is only used in
master mode. The pre-scaled system clock is divided by the baud rate scaler to generate the
frequency of the DSPISCK.
Table 27-8 lists the baud rate scaler values.
The baud rate is computed according to the following equation:
Eqn. 27-4
See Section 27.7.3.1, “Baud Rate Generator ” for more details.
Table 27-6. DSPI Transfer Size
TRSZ Setting
Transfer Size
(in bits)
TRSZ Setting
Transfer Size
(in bits)
0000 Reserved 1000 9
0001 Reserved 1001 10
0010 Reserved 1010 11
0011 4 1011 12
0100 5 1100 13
0101 6 1101 14
0110 7 1110 15
0111 8 1111 16
Table 27-7. Scaler for CS to DSPISCK Delay, After DSPISCK Delay, and Delay After Transfer
CSSCK / ASC / DT
Setting
PCS to DSPISCK
Delay Scaler Value
CSSCK / ASC / DT
Setting
PCS to DSPISCK
Delay Scaler Value
0000 2 1000 512
0001 4 1001 1024
0010 8 1010 2048
0011 16 1011 4096
0100 32 1100 8192
0101 64 1101 16384
Table 27-5. DCTAR Field Descriptions (Continued)
Bits Name Description
t
DT
1
f
sys
-------- PDT DT Ч Ч =
DSPISCK baud rate
f
sys
PBR
------------
1
BR
-------- Ч =