Freescale Semiconductor MCF5480 - Manual (Page 545)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 19-61
The MCF548x can issue PCI configuration transactions to itself. A Type 0 configuration initiated by the
MCF548x can access its own configuration space by asserting its IDSEL input signal.
NOTE
Asserting IDSEL is the only way the MCF548x can clear its own status
register (PCISCR) bits (read-write-clear).
For Type 0 translations, the function number and Dword fields are copied without modification onto the
AD[10:2] signals, and AD[1:0] are driven low during the address phase.
0b0_1011 11 AD11
0b0_1100 12 AD12
0b0_1101 13 AD13
0b0_1110 14 AD14
0b0_1111 15 AD15
0b1_0000 16 AD16
0b1_0001 17 AD17
0b1_0010 18 AD18
0b1_0011 19 AD19
0b1_0100 20 AD20
0b1_0101 21 AD21
0b1_0110 22 AD22
0b1_0111 23 AD23
0b1_1000 24 AD24
0b1_1001 25 AD25
0b1_1010 26 AD26
0b1_1011 27 AD27
0b1_1100 28 AD28
0b1_1101 29 AD29
0b1_1110 30 AD30
0b1_1111 31 -
1 Device numbers 0b0_0000 to 0b0_1001 are reserved. Programming to
these values and issuing a configuration transaction will result in a PCI
configuration cycle with AD31-AD11 driven low.
Table 19-50. Type 0 Configuration Device Number to IDSEL Translation (Continued)
Device Number
IDSEL
Binary Decimal