6 controller, Controller -10 – Freescale Semiconductor MCF5480 User Manual
Page 612

MCF548x Reference Manual, Rev. 3
22-10
Freescale Semiconductor
22.6
Controller
The controller within the SEC core is responsible for overseeing the operations of the EUs, the interface
to the host processor, and the management of the crypto-channels. The controller interfaces to the host via
the bus interface and to the channels and EUs via internal buses.
All transfers between the host and the EUs are moderated by the controller. Some of the main functions of
the controller are as follows:
•
Arbitrate and control accesses to the ColdFire bus
•
Control the internal bus accesses to the EUs
•
Arbitrate and assign EUs to the crypto-channels
•
Monitor interrupts from channels and pass to host
•
Realign initiator read data to 64-bit boundary
DEU Registers
0x2A018
DRCR
DEU Reset Control Register
0x2A028
DSR
DEU Status Register
0x2A030
DISR
DEU Interrupt Status Register
0x2A038
DIMR
DEU Interrupt Mask Register
MDEU Registers
0x2C018
MDRCR
MDEU Reset Control Register
0x2C028
MDSR
MDEU Status Register
0x2C030
MDISR
MDEU Interrupt Status Register
0x2C038
MDIMR
MDEU Interrupt Mask Register
RNG Registers
0x2E018
RRCR
RNG Reset Control Register
0x2E028
RSR
RNG Status Register
0x2E030
RISR
RNG Interrupt Status Register
0x2E038
RIMR
RNG Interrupt Mask Register
AESU Registers
0x32018
AESRCR
AESU Reset Control Register
0x32028
AESSR
AESU Status Register
0x32030
AESISR
AESU Interrupt Status Register
0x32038
AESIMR
AESU Interrupt Mask Register
Table 22-3. SEC Register Map (Continued)
Register
Offset
Mnemonic
Name
Page