Freescale Semiconductor MCF5480 - Manual (Page 886)

MCF548x Reference Manual, Rev. 3
29-12 Freescale Semiconductor
29.2.2.3 USB Descriptor RAM Control Register (DRAMCR)
1 APPLOCK Application Lock. This bit should be asserted to ensure the indivisibility of read-modify-write (RMW)
operations on certain USB 2.0 device registers. Many register bits can be written to by the user
software and the internal logic. Collisions between these two agents can occur when the user
software is performing a RMW operation on any of these register bits while the internal logic tries to
update the same bit(s) between the read cycle and the write cycle of the user software. For RMW
operations, the user software should set this bit before the read and clear it after the completion of
the write.
The register bits that require this "locked" RMW operation are:
USBAISR[7:0]
EPnOUTSR/EPnINSR[5]
EPnOUTSR/EPnINSR[3:2]
EPnOUTSR/EPnINSR[0]
CFGAR[6]
0 APPLOCK is deasserted.
1 APPLOCK is asserted.
0 RESUME Resume. This initiates resume signalling on the USB. If remote wake-up capability is enabled for the
current USB configuration, writing a 1 to this bit will cause the USB module to initiate resume
signalling on the bus. This bit automatically resets to 0 after a write. Writing a 0 to this bit has no
effect. If remote wake-up capability has been disabled in the USB via the CLEAR_FEATURE
request, then this bit will have no effect. Any user software should have a time-out feature that aborts
the remote wake-up attempt after some time if the RESUME interrupt does not occur.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 BSY Uninitialized DSIZE
W START
Reset 0 0 Uninitialized 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Uninitialized DADR
W
Reset Uninitialized 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0xB408
Figure 29-4. USB Descriptor RAM Control Register (DRAMCR)
Table 29-3. USBCR Field Descriptions (Continued)
Bits Name Description