Freescale Semiconductor MCF5480 - Manual (Page 554)

MCF548x Reference Manual, Rev. 3
19-70 Freescale Semiconductor
19.4.6.9 Bus Errors
Because bus errors are particular to the module register set and that register set includes both transmit and
receive controller and FIFO settings, the bus error status bits and Bus error Enable bit(s) are duplicated in
the Transmit and Receive register groupings. Clearing or setting one will clear or set the other. From a
software point of view, then, they can be treated separately or together, as desired.
19.4.7 PCI Clock Scheme
The MCF548x requires a clock generated by an external PLL to be input to the CLKIN signal in order to
generate an internal PCI clock. The MCF548x uses this clock as its reference clock. The internal PLL
generates the internal PCI clock and all other clocks for the system. The PCI Global Status/Control
Register on page 14 reflects the PLL programmed ratios.
The PCI bus clock to external PCI devices is generated from an external PLL, while the internal PCI clock
is generated from the MCF548x internal PLL. The XL bus is always faster than the PCI clock.
19.4.8 Interrupts
19.4.8.1 PCI Bus Interrupts
MCF548x does not generate interrupts on the PCI bus interrupt lines INTA - INTD.
19.4.8.2 Internal Interrupt
The PCI module is capable of generating three interrupts to MCF548x interrupt controller in MCF548x
SIU. Each interrupt can be enabled for a variety of conditions, mostly error conditions. For the XL bus
Initiator interface, the internal interrupt can be enabled for Retry errors, Target Aborts and Initiator
(Master) Aborts. See Section 19.3.2.9, “Initiator Control Register (PCIICR),” and Section 19.3.2.10,
“Initiator Status Register (PCIISR),” for more information. For the comm bus Initiator interface, an
internal interrupt can be enabled for FIFO errors and Normal Termination of a packet transfer for either
the Receive (Rx) or Transmit (Tx) interface. For more information, see the enable and status registers for
the comm bus transmit and receive interfaces, Section 19.3.3.1, “Comm Bus FIFO Transmit Interface,”
and Section 19.4, “Functional Description.”
19.5 Application Information
This section provides example usage of some of the features of the PCI module.
19.5.1 XL Bus-Initiated Transaction Mapping
The use of the PCI configuration address register along with the initiator window registers provide many
possibilities for PCI command and address generation. Table 19-57 shows how the PCI Controller accepts
Table 19-56. PCI and System Clock Frequencies
CLKIN PCI CLK XL Bus CLK CPU Core CLK
XL Bus
Multiplier
25 MHz 25 MHz 100 MHz 200 MHz 4
25-50 MHz 25-50 MHz 50-100 MHz 100-200 MHz 2