Freescale Semiconductor MCF5480 - Manual (Page 6)

MCF548x Reference Manual, Rev. 3
vi Freescale Semiconductor
Contents
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Number
Title
Page
Number
2.2.1.4 Read/Write (R/W) ................................................................................................. 2-17
2.2.1.5 Transfer Burst (TBST) .......................................................................................... 2-17
2.2.1.6 Transfer Size (TSIZ[1:0]) ..................................................................................... 2-17
2.2.1.7 Byte Selects (BE/BWE[3:0]) ................................................................................ 2-18
2.2.1.8 Output Enable (OE) .............................................................................................. 2-18
2.2.1.9 Transfer Acknowledge (TA) ................................................................................. 2-18
2.2.2 SDRAM Controller Signals ...................................................................................... 2-18
2.2.2.1 SDRAM Data Bus (SDDATA[31:0]) ................................................................... 2-18
2.2.2.2 SDRAM Address Bus (SDADDR[12:0]) ............................................................. 2-18
2.2.2.3 SDRAM Bank Addresses (SDBA[1:0]) ............................................................... 2-19
2.2.2.4 SDRAM Row Address Strobe (RAS) ................................................................... 2-19
2.2.2.5 SDRAM Column Address Strobe (CAS) ............................................................. 2-19
2.2.2.6 SDRAM Chip Selects (SDCS[3:0]) ...................................................................... 2-19
2.2.2.7 SDRAM Write Data Byte Mask (SDDM[3:0]) .................................................... 2-19
2.2.2.8 SDRAM Data Strobe (SDDQS[3:0]) .................................................................... 2-19
2.2.2.9 SDRAM Clock (SDCLK[1:0]) ............................................................................. 2-19
2.2.2.10 Inverted SDRAM Clock (SDCLK[1:0]) ............................................................... 2-19
2.2.2.11 SDRAM Write Enable (SDWE) ........................................................................... 2-19
2.2.2.12 SDRAM Clock Enable (SDCKE) ......................................................................... 2-19
2.2.2.13 SDR SDRAM Data Strobe (SDRDQS) ................................................................ 2-19
2.2.2.14 SDRAM Reference Voltage (VREF) ................................................................... 2-20
2.2.3 PCI Controller Signals .............................................................................................. 2-20
2.2.3.1 PCI Address/Data Bus (PCIAD[31:0]) ................................................................. 2-20
2.2.3.2 Command/Byte Enables (PCICXBE[3:0]) ........................................................... 2-20
2.2.3.3 Device Select (PCIDEVSEL) ............................................................................... 2-20
2.2.3.4 Frame (PCIFRM) .................................................................................................. 2-20
2.2.3.5 Initialization Device Select (PCIIDSEL) .............................................................. 2-20
2.2.3.6 Initiator Ready (PCIIRDY) ................................................................................... 2-20
2.2.3.7 Parity (PCIPAR) ................................................................................................... 2-20
2.2.3.8 Parity Error (PCIPERR) ....................................................................................... 2-20
2.2.3.9 Reset (PCIRESET) ............................................................................................... 2-21
2.2.3.10 System Error (PCISERR) ..................................................................................... 2-21
2.2.3.11 Stop (PCISTOP) ................................................................................................... 2-21
2.2.3.12 Target Ready (PCITRDY) .................................................................................... 2-21
2.2.3.13 External Bus Grant (PCIBG[4:1]) ........................................................................ 2-21
2.2.3.14 External Bus Grant/Request Output (PCIBG0/PCIREQOUT) ............................ 2-21
2.2.3.15 External Bus Request (PCIBR[4:0]) ..................................................................... 2-21
2.2.3.16 External Request/Grant Input (PCIBR0/PCIGNTIN) .......................................... 2-21
2.2.4 Interrupt Control Signals .......................................................................................... 2-21
2.2.4.1 Interrupt Request (IRQ[7:1]) ................................................................................ 2-21
2.2.5 Clock and Reset Signals ........................................................................................... 2-22