Freescale Semiconductor MCF5480 - Manual (Page 269)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 8-19
28 EDLW2 Data enable bit: Data longword. Entire processor’s local data bus.
27 EDWL2 Data enable bit: Lower data word.
26 EDWU2 Data enable bit: Upper data word.
25 EDLL2 Data enable bit: Lower lower data byte. Low-order byte of the low-order word.
24 EDLM2 Data enable bit: Lower middle data byte. High-order byte of the low-order word.
23 EDUM2 Data enable bit: Upper middle data byte. Low-order byte of the high-order word.
22 EDUU2 Data enable bit: Upper upper data byte. High-order byte of the high-order word.
21 DI2 Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value other than the
DBR contents.
20 EAI2 Address enable bit: Enable address breakpoint inverted. Breakpoint is based outside the range
between ABLR and ABHR. Trigger if address > ABHR or if address < ABLR.
19 EAR2 Address enable bit: Enable address breakpoint range. The breakpoint is based on the inclusive
range defined by ABLR and ABHR. Trigger if address Š ABHR or if address ð ABLR.
18 EAL2 Address enable bit: Enable address breakpoint low. The breakpoint is based on the address in the
ABLR. Trigger address = ABLR
17 EPC2 Enable PC breakpoint. If set, this bit enables the PC breakpoint for the second level trigger.
16 PCI2 Breakpoint invert. If set, this bit allows execution outside a given region as defined by
PBR/PBR1/PBR2/PBR3 and PBMR to enable a trigger. If cleared, the PC breakpoint is defined
within the region defined by PBR/PBR1/PBR2/PBR3 and PBMR.
15–14 — Reserved, should be cleared.
13 EBL1 Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] or XTDR[EBL]
enables a breakpoint trigger. If both TDL[EBL] and XTDL[EBL] are cleared, all breakpoints are
disabled.
12 EDLW1 Data enable bit: Data longword. Entire processor’s local data bus.
11 EDWL1 Data enable bit: Lower data word.
10 EDWU1 Data enable bit: Upper data word.
9 EDLL1 Data enable bit: Lower lower data byte. Low-order byte of the low-order word.
8 EDLM1 Data enable bit: Lower middle data byte. High-order byte of the low-order word.
7 EDUM1 Data enable bit: Upper middle data byte. Low-order byte of the high-order word.
6 EDUU1 Data enable bit: Upper upper data byte. High-order byte of the high-order word.
5 DI1 Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value other than the
DBR contents.
4 EAI1 Address enable bit: Enable address breakpoint inverted. Breakpoint is based outside the range
between ABLR and ABHR. Trigger if address > ABHR or if address < ABLR.
3 EAR1 Address enable bit: Enable address breakpoint range. The breakpoint is based on the inclusive
range defined by ABLR and ABHR. Trigger if address Š ABHR or if address ð ABLR.
Table 8-12. TDR Field Descriptions (Continued)
Bits Name Description