Freescale Semiconductor MCF5480 User Manual
Page 622
MCF548x Reference Manual, Rev. 3
22-20
Freescale Semiconductor
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R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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14
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11
10
9
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5
4
3
2
1
0
R
0
0
0
0
0
BURST_SIZE
0
0
0
WE
NE
NT
CDIE RST
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x2200C (CCCR0), 0x2300C (CCCR1)
Figure 22-16. Crypto-Channel Configuration Register (CCCRn)
Table 22-11. CCCRn Field Descriptions
Bits
Name
Description
31–11
—
Reserved, should be cleared.
10–8
BURST SIZE The SEC implements flow control to allow larger than FIFO sized blocks of data to be
processed with a single key/IV. The channel programs the various execution units to advise on
space or data available in the FIFO via this field. The size of the burst is given in
7–5
—
Reserved, should be cleared.
4
WE
Writeback Enable. This bit determines if the crypto-channel is allowed to notify the host of the
completion of descriptor processing by writing back a value of 0xFF to the first byte of the
descriptor header. This enables the host to poll the memory location of the original descriptor
header to determine if that descriptor has been completed.
0 Descriptor header writeback notification is disabled.
1 Descriptor header writeback notification is enabled.
Note: Header writeback notification will occur at the end of every descriptor if
NOTIFICATION_TYPE is set to end-of-descriptor and Writeback_Enable is set. Writeback will
occur only after the last descriptor in the chain (Next Descriptor Pointer is NULL) if
NOTIFICATION_TYPE is set to end-of-chain.
3
NE
Fetch Next Descriptor Enable. This bit determines if the crypto-channel is allowed to request
a transfer of the next descriptor, in a multi-descriptor chain, into its descriptor buffer.
0 Disable fetching of next descriptor when crypto-channel has finished processing the current
one.
1 Enable fetching of next descriptor when crypto-channel has finished processing the current
one.
The address of the next descriptor in a multi-descriptor chain is either the contents of the next
descriptor pointer in the descriptor buffer or the contents of the fetch register. Only if both of
these registers are NULL upon completion of the descriptor currently being processed will that
descriptor be considered the end of the chain.