Freescale Semiconductor MCF5480 User Manual
Page 941
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
30-11
Interrupts resulting from errors/problems detected in the network or transceiver are HBERR, BABR,
BABT, LC, and RL. Interrupts resulting from internal errors are HBERR, XFUN, XFERR, and RFERR.
Some of the error interrupts are independently counted in the MIB block counters. Software may choose
to mask off these interrupts because these errors will be visible to network management via the MIB
counters.
•
HBERR – IEEE_T_SQE
•
BABR – RMON_R_OVERSIZE (good CRC), RMON_R_JAB (bad CRC)
•
BABT – RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC)
•
LC – IEEE_T_LCOL
•
RL – IEEE_T_EXCOL
•
XFUN – IEEE_T_MACERR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R HBERR BABR BABT GRA
TXF
0
0
0
MII
0
LC
RL
XFUN XFERR RFERR
0
W
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x9004 (FEC0), 0x9804 (FEC1)
Figure 30-2. Ethernet Interrupt Event
Register (EIR)
Table 30-7. EIR Descriptions
Bits
Name
Description
31
HBERR
Heartbeat error. This interrupt indicates that HBC is set in the TCR register and that the ECOL input
was not asserted within the Heartbeat window following a transmission. This bit is cleared by writing
a 1 to it.
30
BABR
Babbling receive error. This bit indicates a frame was received with length in excess of
RCR[MAX_FL] bytes. This bit is cleared by writing a 1 to it.
29
BABT
Babbling transmit error. This bit indicates that the transmitted frame length has exceeded
RCR[MAX_FL] bytes. This condition is usually caused by a frame that is too long being placed into
the transmit data buffers. Truncation does not occur. This bit is cleared by writing a 1 to it.
28
GRA
Graceful stop complete. This interrupt will be asserted for one of three reasons. Graceful stop
means that the transmitter is put into a pause state after completion of the frame currently being
transmitted.
1) A graceful stop, which was initiated by the setting of the TCR[GTS] bit is now complete.
2) A graceful stop, which was initiated by the setting of the TCR[TFC_PAUSE] bit is now complete.
3) A graceful stop, which was initiated by the reception of a valid full duplex flow control “pause”
frame is now complete. Refer to
Section 30.4.8, “Full Duplex Flow Control
This bit is cleared by writing a 1 to it.
27
TXF
Transmit frame interrupt. This bit indicates that a frame has been transmitted. This bit is cleared by
writing a 1 to it.