Freescale Semiconductor MCF5480 - Manual (Page 449)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 18-1
Chapter 18
SDRAM Controller (SDRAMC)
18.1 Introduction
This chapter describes configuration and operation of the synchronous DRAM (SDRAM) controller. It
begins with a general overview and includes a description of signals involved in SDRAM operations. The
remainder of the chapter describes the programming model and signal timing, as well as the command set
required for synchronous DRAM operations. It also includes examples that the designer can follow to
better understand how to configure the SDRAM controller for synchronous operations.
18.2 Overview
18.2.1 Features
The MCF548x SDRAM controller contains the following features:
• Supports a glueless interface to SDR and DDR SDRAMs
• 32-bit fixed memory port width
• 64-bit data bus interface to internal XLB 64-bit bus
• 32 bytes critical word first burst transfer
• Up to 13 row address lines, up to 12 column address lines, 2 bits of bank address, and a maximum
of four chip selects. The maximum row bits plus column bits can be less than or equal to 24.
• Supports up to 1 Gbyte of memory—13+11 or 12+12 bit RA+CA, 2 bit BA, four chip selects
• Minimum memory configuration of 8 Mbyte—11 bit row address (RA), 8 bit column address
(CA), 2 bit bank address (BA) and one chip select
• Supports page mode to maximize the data rate
• Supports sleep mode and self-refresh mode
• Error detect and parity check are not supported
18.2.2 Terminology
The following terminology is used in this chapter:
• SDRAM block: Any group of DRAM memories selected by one of the MCF548x SDCS[3:0]
signals. Thus, the MCF548x can support up to four independent memory blocks. The base address
of each block is programmed in the DRAM address and control registers (DACR0 and DACR1).
• SDRAM bank: An internal partition in an SDRAM device. For example, a 64-Mbit SDRAM
component might be configured as four 512K x 32 banks. Banks are selected through the
SD_BA[1:0] signals.
• SDRAM: These are RAMs that operate like asynchronous DRAMs but with a synchronous clock,
a pipelined, multiple-bank architecture, and a faster speed.
• Single data rate (SDR) SDRAM: This is SDRAM that drives/latches data and command
information on the rising edge of the clock.
• Double data rate (DDR) SDRAM: This is SDRAM that latches command information on the rising
edge of the clock, but data is driven/latched on both the rising and falling edges of the clock rather
than on just the rising edge. This doubles data throughput rate without an increase in frequency.