Freescale Semiconductor MCF5480 - Manual (Page 974)

MCF548x Reference Manual, Rev. 3
30-44 Freescale Semiconductor
30.4.2 Frame Control/Status Words
In the FEC, transmit frame control words and receive frame status words are appended to frame data in the
FIFO. These words use the format shown below.
30.4.2.1 Receive Frame Status Word (RFSW)
Figure 30-39 defines the format for the receive frame status word.
Set MSCR (optional)
Clear MIB RAM (locations MBAR + 0x9200–0x92E3 and
MBAR + 0x9A00–0x9AE3)
Reset Comm Bus FIFOs in the FIFO Reset register
Set Comm Bus FIFO Alarm and Control Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field — L — M BC MC LG NO — CR OF TR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field — FRAME_LENGTH
Figure 30-39. Receive Frame Status Word Format (RFSW)
Table 30-45. RFSW Field Descriptions
Bits Name Description
31–28 — Reserved, should be cleared.
27 L Last in frame. Written by the FEC.
0 The buffer is not the last in a frame
1 The buffer is the last in a frame
26–25 — Reserved, should be cleared.
24 M Miss. Written by the FEC. This bit is set by the FEC for frames that were acccepted in
promiscuous mode, but were flagged as a “miss” by the internal address recognition. Thus,
while in promiscuous mode, the user can use the M-bit to quickly determine whether the
frame was destined to this station. This bit is valid only if the L-bit is set and the PROM bit
is set.
0 The frame was received because of an address recognition hit.
1 The frame was received because of promiscuous mode.
23 BC Will be set if the destination address (DA) is broadcast (FF-FF-FF-FF-FF-FF).
22 MC Will be set if the DA is multicast and not BC.
21 LG Receive frame length Violation. Written by the FEC. A frame length greater than
RCR[MAX_FL] was recognized. This bit is valid only if the L-bit is set. The receive data is
not altered in any way unless the length exceeds 2047 bytes.
Table 30-44. User Initialization (Before Asserting ECR[ETHER_EN]) (Continued)
Description