3 deu status register (dsr), Deu status register (dsr) -35, P. 22-35 – Freescale Semiconductor MCF5480 User Manual
Page 637
Data Encryption Standard Execution Units (DEU)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
22-35
Figure 22-25. DEU Reset Control Register (DRCR)
describes DEU reset control register fields.
22.9.3
DEU Status Register (DSR)
This status register, displayed in
, contains 6 bits which reflect the state of DEU internal
signals.
The DEU status register is read-only. Writing to this location will result in address error being reflected in
the DEU interrupt status register.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
RI
MI
SR
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x2A018
Table 22-22. DRCR Field Descriptions
Bits
Names
Description
31–27
—
Reserved
26
RI
Reset interrupt. Writing this bit active high causes DEU interrupts signalling DONE and
ERROR to be reset. It further resets the state of the DEU interrupt status register.
0 Don’t reset
1 Reset interrupt logic
25
MI
Module initialization is nearly the same as software reset, except that the interrupt control
register remains unchanged. this module initialization includes execution of an initialization
routine, completion of which is indicated by the RD bit in the DEU status register
0 Don’t reset
1 Reset most of DEU
24
SR
Software reset is functionally equivalent to hardware reset (the RSTI pin), but only for DEU.
All registers and internal state are returned to their defined reset state. After the reset
completes, the DEU will enter a routine to perform proper initialization of the parameter
memories. The RD bit in the DEU status register will indicate when this initialization routine
is complete
0 Don’t reset
1 Full DEU reset
23-0
—
Reserved