Freescale Semiconductor MCF5480 - Manual (Page 753)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 25-1
Chapter 25
Comm Timer Module (CTM)
25.1 Introduction
This chapter contains a detailed description of the Comm Timer Module (CTM).
25.1.1 Block Diagrams
The following section presents three block diagrams showing the CTM in greater detail. Figure 25-1 is a
high level block diagram of the CTM. The figure shows the signal flow through the sub-modules and the
architecture on a high level.
Figure 25-1. CTM High Level Block Diagram
Figure 25-2 and Figure 25-3 are conceptual block diagrams of the fixed timer channel and variable timer
channel respectively. These diagrams are more detailed than earlier diagrams but should still be considered
a conceptual illustration of the actual hardware implementations.
cAcknowledge[7:0]
cInitiator
Synchronizer
Register Timer
Variable
TimerChannel[0]
Register Timer
Fixed
TimerChannel[0]
Write/Read
Enable
Logic
Addr
Decode
Logic
8-bit
Prescaler
externalClkIn[7:0]
clk
cAcknowledge[7:0]
Register Timer
Variable
TimerChannel[n]
Register Timer
Fixed
TimerChannel[n]
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•
•
•
•
•
•
timerInterrupt
cInitiator
Comm Timer
Module
Internal Data_bus
•
•
•
•
•
•
•
Internal
Bus