Freescale Semiconductor MCF5480 - Manual (Page 31)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor xxxi
Contents
Paragraph
Number
Title
Page
Number
26.1.1 Block Diagram .......................................................................................................... 26-1
26.1.2 Overview ................................................................................................................... 26-1
26.1.3 Features ..................................................................................................................... 26-1
26.1.4 Modes of Operation .................................................................................................. 26-1
26.2 Signal Description ......................................................................................................... 26-2
26.2.1 PSCnCTS/PSCBCLK ............................................................................................... 26-2
26.2.2 PScnrts/pscfsync ....................................................................................................... 26-2
26.2.3 PSCnrxd .................................................................................................................... 26-2
26.2.4 pscntxd ...................................................................................................................... 26-3
26.2.5 Signal Properties in Each Mode ................................................................................ 26-3
26.3 Memory Map/Register Definition ................................................................................ 26-3
26.3.1 Overview ................................................................................................................... 26-3
26.3.2 Module Memory Map ............................................................................................... 26-3
26.3.3 Register Descriptions ................................................................................................ 26-5
26.3.3.1 Mode Register 1(PSCMR1n) ................................................................................ 26-5
26.3.3.2 Mode Register 2 (PSCMR2n) ............................................................................... 26-6
26.3.3.3 Status Register (PSCSRn) ..................................................................................... 26-8
26.3.3.4 Clock Select Register (PSCCSRn) ..................................................................... 26-10
26.3.3.5 Command Register (PSCCRn) ........................................................................... 26-11
26.3.3.6 Receiver Buffer (PSCRBn) and Transmitter Buffer (PSCTBn) ......................... 26-14
26.3.3.7 Input Port Change Register (PSCIPCRn) ........................................................... 26-17
26.3.3.8 Auxiliary Control Register (PSCACRn) ............................................................ 26-18
26.3.3.9 Interrupt Status Register (PSCISRn) .................................................................. 26-18
26.3.3.10 Interrupt Mask Register (PSCIMRn) .................................................................. 26-19
26.3.3.11 Counter Timer Registers (PSCCTURn, PSCCTLRn) ........................................ 26-21
26.3.3.12 Input Port (PSCIPn) ............................................................................................ 26-21
26.3.3.13 Output Port Bit Set (PSCOPSETn) ..................................................................... 26-22
26.3.3.14 Output Port Bit Reset (PSCOPRESETn) ............................................................ 26-22
26.3.3.15 PSC/IrDA Control Register (PSCSICRn) .......................................................... 26-23
26.3.3.16 Infrared Control Register 1 (PSCIRCR1n) ......................................................... 26-24
26.3.3.17 Infrared Control Register 2 (PSCIRCR2n) ......................................................... 26-24
26.3.3.18 Infrared SIR Divide Register (PSCIRSDRn) ..................................................... 26-25
26.3.3.19 Infrared MIR Divide Register (PSCIRMDRn) ................................................... 26-25
26.3.3.20 Infrared FIR Divide Register (PSCIRFDRn) ..................................................... 26-26
26.3.3.21 Rx and Tx FIFO Counter Register (PSCRFCNTn, PSCTFCNTn) .................... 26-27
26.3.3.22 Rx and Tx FIFO Data Register (PSCRFDRn, PSCTFDRn) .............................. 26-27
26.3.3.23 Rx and Tx FIFO Status Register (PSCRFSRn, PSCTFSRn) ............................. 26-28
26.3.3.24 Rx and Tx FIFO Control Register (PSCRFCRn, PSCTFCRn) .......................... 26-30
26.3.3.25 Rx and Tx FIFO Alarm Register (PSCRFARn, PSCTFARn) ............................ 26-32
26.3.3.26 Rx and Tx FIFO Read Pointer (PSCRFRPn, PSCTFRPn) ................................. 26-32
26.3.3.27 Rx and Tx FIFO Write Pointer (PSCRFWPn, PSCTFWPn) .............................. 26-33