Freescale Semiconductor MCF5480 - Manual (Page 644)

MCF548x Reference Manual, Rev. 3
22-42 Freescale Semiconductor
Figure 22-30. MDEU Status Register (MDSR)
Table 22-27 describes MDEU status register fields.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 HALT IFW 0 IE ID RD 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0x2C028
Table 22-27. MDSR Field Descriptions
Bits Name Description
31-30 — Reserved, should be cleared.
229 HALT Halt. Indicates that the MDEU has halted due to an error.
0 MDEU not halted
1 MDEU halted
Note: Because the error causing the MDEU to stop operating may be masked to the
interrupt status register, the status register is used to provide a second source of
information regarding errors preventing normal operation.
28 IFW Input FIFO Writable. The controller uses this signal to determine if the MDEU can accept
the next BURST SIZE block of data.
0 MDEU Input FIFO not ready
1 MDEU Input FIFO ready
Note: The SEC implements flow control to allow larger than FIFO sized blocks of data to
be processed with a single key/IV. The MDEU signals to the crypto-channel that a ‘burst
size’ amount of space is available in the FIFO. The documentation of this bit in the MDEU
status register is to avoid confusing a user who may read this register in debug mode.
27 — Reserved, should be cleared
26 IE Interrupt Error. This status bit reflects the state of the ERROR interrupt signal, as sampled
by the controller interrupt status register (
Section 22.6.4.4, “SEC Interrupt Status Registers
(SISRH and SISRL) ”).
0 MDEU is not signaling error
1 MDEU is signaling error
25 ID Interrupt Done. This status bit reflects the state of the DONE interrupt signal, as sampled
by the controller interrupt status register (
Section 22.6.4.4, “SEC Interrupt Status Registers
(SISRH and SISRL) ”).
0 MDEU is not signaling done
1 MDEU is signaling done