Freescale Semiconductor MCF5480 - Manual (Page 18)

MCF548x Reference Manual, Rev. 3
xviii Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
15.4 Functional Description ................................................................................................ 15-32
15.4.1 Overview ................................................................................................................. 15-32
Chapter 16
32-Kbyte System SRAM
16.1 Introduction ................................................................................................................... 16-1
16.1.1 Block Diagram .......................................................................................................... 16-1
16.1.2 Features ..................................................................................................................... 16-2
16.1.3 Overview ................................................................................................................... 16-2
16.2 Memory Map/Register Definition ................................................................................ 16-2
16.2.1 System SRAM Configuration Register (SSCR) ....................................................... 16-3
16.2.2 Transfer Count Configuration Register (TCCR) ..................................................... 16-4
16.2.3 Transfer Count Configuration Register—DMA Read Channel (TCCRDR) ............ 16-5
16.2.4 Transfer Count Configuration Register—DMA Write Channel (TCCRDW) .......... 16-6
16.2.5 Transfer Count Configuration Register—SEC (TCCRSEC) .................................... 16-7
16.3 Functional Description .................................................................................................. 16-8
Chapter 17
FlexBus
17.1 Introduction ................................................................................................................... 17-1
17.1.1 Overview ................................................................................................................... 17-1
17.1.2 Features ..................................................................................................................... 17-1
17.1.3 Modes of Operation .................................................................................................. 17-1
17.2 Byte Lanes .................................................................................................................... 17-2
17.3 Address Latch ............................................................................................................... 17-2
17.4 External Signals ............................................................................................................ 17-3
17.4.1 Chip-Select (FBCS[5:0]) .......................................................................................... 17-4
17.4.2 Address/Data Bus (AD[31:0]) .................................................................................. 17-4
17.4.3 Address Latch Enable (ALE) .................................................................................... 17-4
17.4.4 Read/Write (R/W) ..................................................................................................... 17-4
17.4.5 Transfer Burst (TBST) .............................................................................................. 17-4
17.4.6 Transfer Size (TSIZ[1:0]) ......................................................................................... 17-4
17.4.7 Byte Selects (BE/BWE[3:0]) .................................................................................... 17-5
17.4.8 Output Enable (OE) .................................................................................................. 17-5
17.4.9 Transfer Acknowledge (TA) ..................................................................................... 17-5
17.5 Chip-Select Operation ................................................................................................... 17-6
17.5.1 General Chip-Select Operation ................................................................................. 17-6
17.5.1.1 8-, 16-, and 32-Bit Port Sizing .............................................................................. 17-6