Freescale Semiconductor MCF5480 - Manual (Page 26)

MCF548x Reference Manual, Rev. 3
xxvi Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
22.6.4.8 Master Error Address Register (MEAR) ............................................................ 22-18
22.7 Channels ...................................................................................................................... 22-18
22.7.1 Crypto-Channel Registers ....................................................................................... 22-19
22.7.1.1 Crypto-Channel Configuration Registers (CCCRn) ........................................... 22-19
22.7.1.2 Crypto-Channel Pointer Status Registers (CCPSRHn and CCPSRLn) .............. 22-21
22.7.1.3 Crypto-Channel Current Descriptor Pointer Register (CDPRn) ........................ 22-27
22.7.1.4 Fetch Register (FRn) ........................................................................................... 22-27
22.7.1.5 Data Packet Descriptor Buffer (CDBUFn) ......................................................... 22-28
22.8 ARC Four Execution Unit (AFEU) ............................................................................ 22-28
22.8.1 AFEU Register Map ............................................................................................... 22-28
22.8.2 AFEU Reset Control Register (AFRCR) ................................................................ 22-28
22.8.3 AFEU Status Register (AFSR) ............................................................................... 22-29
22.8.4 AFEU Interrupt Status Register (AFISR) ............................................................... 22-31
22.8.5 AFEU Interrupt Mask Register (AFIMR) .............................................................. 22-32
22.9 Data Encryption Standard Execution Units (DEU) .................................................... 22-34
22.9.1 DEU Register Map .................................................................................................. 22-34
22.9.2 DEU Reset Control Register (DRCR) .................................................................... 22-34
22.9.3 DEU Status Register (DSR) .................................................................................... 22-35
22.9.4 DEU Interrupt Status Register (DISR) ................................................................... 22-37
22.9.5 DEU Interrupt Mask Register (DIMR) ................................................................... 22-39
22.10 Message Digest Execution Unit (MDEU) .................................................................. 22-40
22.10.1 MDEU Register Map .............................................................................................. 22-40
22.10.2 MDEU Reset Control Register (MDRCR) ............................................................. 22-41
22.10.3 MDEU Status Register (MDSR) ............................................................................. 22-41
22.10.4 MDEU Interrupt Status Register (MDISR) ............................................................ 22-43
22.10.5 MDEU Interrupt Mask Register (MDIMR) ............................................................ 22-44
22.11 RNG Execution Unit (RNG) ...................................................................................... 22-46
22.11.1 RNG Register Map ................................................................................................. 22-46
22.11.2 RNG Reset Control Register (RNGRCR) .............................................................. 22-46
22.11.3 RNG Status Register (RNGSR) .............................................................................. 22-47
22.11.4 RNG Interrupt Status Register (RNGISR) .............................................................. 22-48
22.11.5 RNG Interrupt Mask Register (RNGIMR) ............................................................. 22-49
22.12 Advanced Encryption Standard Execution Units (AESU) ....................................... 22-50
22.12.1 AESU Register Map ............................................................................................... 22-50
22.12.2 AESU Reset Control Register (AESRCR) ............................................................. 22-50
22.12.3 AESU Status Register (AESSR) ............................................................................. 22-51
22.12.4 AESU Interrupt Status Register (AESISR) ............................................................ 22-53
22.12.5 AESU Interrupt Mask Register (AESIMR) ............................................................ 22-54
22.13 Descriptors .................................................................................................................. 22-56
22.13.1 Descriptor Structure ................................................................................................ 22-56
22.13.1.1 Descriptor Header ............................................................................................... 22-57