Freescale Semiconductor MCF5480 - Manual (Page 441)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 17-25
Figure 17-24. Read Cycle with Two Clock Address Hold (No Wait States)
Figure 17-25. Write Cycle with Two Clock Address Hold (No Wait States)
Figure 17-26 shows a bus cycle that uses address setup, wait states, and address hold.
CLK
AD[X:0]
AD[31:Y]
R/W
ALE
TA
OE
S0 S1 S2 S3 AH
FBCSn, BE/BWEn
ADDR[X:0]
A[31:Y] DATA
TSIZ[1:0] TSIZ[1:0]
CLK
AD[X:0]
AD[31:Y]
R/W
ALE
TA
OE
S0 S1 S2 S3 AH
FBCSn, BE/BWEn
ADDR[X:0]
A[31:Y] DATA
TSIZ[1:0] TSIZ[1:0]