5 cache locking, Cache locking -17 – Freescale Semiconductor MCF5480 User Manual
Page 237
Cache Operation
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
7-17
7.9.5
Cache Locking
Ways 0 and 1 of the data cache can be locked by setting CACR[DHLCK]; likewise, ways 0 and 1 of the
instruction cache can be locked by setting CACR[IHLCK]. If a cache is locked, cache lines in ways 0 and
1 are not subject to being deallocated by normal cache operations.
As
(B and C) shows, the algorithm for updating the cache and for identifying cache lines to be
deallocated is otherwise unchanged. If ways 2 and 3 are entirely invalid, cacheable accesses are first
allocated in way 2. Way 3 is not used until the location in way 2 is occupied.
Ways 0 and 1 are still updated on write hits (D in
) and may be pushed or cleared only explicitly
by using specific cache push/invalidate instructions. However, new cache lines cannot be allocated in ways
0 and 1.