Freescale Semiconductor MCF5480 - Manual (Page 420)

MCF548x Reference Manual, Rev. 3
17-4 Freescale Semiconductor
17.4.1 Chip-Select (FBCS[5:0])
The chip-select signal indicates which device is being selected. A particular chip-select asserts when the
transfer address is within the device’s address space as defined in the base and mask address registers, see
Section 17.5.2, “Chip-Select Registers .”
17.4.2 Address/Data Bus (AD[31:0])
The AD[31:0] bus carries address and data. The full 32-bit address is always driven on the first clock of a
bus cycle (address phase). The number of byte lanes used to carry the data during the data phase is
determined by the port size associated with the matching chip select.
In non-multiplexed mode, it is divided into sub-buses: address (output) and data (input/output). In
multiplexed mode, it carries the address during the address phase and the data during the data phase. Note
that in multiplexed mode and during the data phase, the address continues driving on the lower byte lanes
if these lanes are not used to carry the data.
17.4.3 Address Latch Enable (ALE)
The assertion of ALE indicates that the MCF548x has begun a bus transaction and that the address and
attributes are valid. ALE is asserted for one bus clock cycle. In multiplexed bus mode, ALE is used
externally as an address latch enable to capture the address phase of the bus transfer, as shown in
Figure 17-2 .
17.4.4 Read/Write (R/W)
MCF548x drives the R/W signal to indicate the direction of the current bus operation. It is driven high
during read bus cycles and driven low during write bus cycles.
17.4.5 Transfer Burst (TBST)
Transfer Burst indicates that a burst transfer is in progress as driven by the MCF548x. A burst transfer can
be 2 to 16 beats depending on TSIZ[1:0] and the port size.
NOTE
When burst (TBST = 0) and transfer size is 16 bytes (TSIZ = 2’b11) and the
address is misaligned within the 16-byte boundary, the external device must
be able to wrap around the address.
17.4.6 Transfer Size (TSIZ[1:0])
For memory accesses, these signals, along with TBST, indicate the data transfer size of the current bus
operation. The FlexBus interface supports byte, word, and longword operand transfers and allows accesses
to 8-, 16-, and 32-bit data ports.
For misaligned transfers, TSIZ[1:0] indicate the size of each transfer. For example, if a longword access
through a 32-bit port device occurs at a misaligned offset of 0x1, a byte is transferred first
(TSIZ[1:0] = 01), a word is next transferred at offset 0x2 (TSIZ[1:0] = 10), then the final byte is
transferred at offset 0x4 (TSIZ[1:0] = 01).