Freescale Semiconductor MCF5480 - Manual (Page 133)

Instruction Execution Timing
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 3-29
Table 3-12 lists timings for MOVE.L.
Table 3-13 gives timings for MOVE.L instructions accessing program-visible EMAC registers, along with
other MOVE.L timings. Execution times for moving ACC or MACSR contents into a destination location
represent the best-case scenario when the store instruction is executed and no load, MAC, or MSAC
instructions are in the EMAC execution pipeline. In general, these store operations take only 1 cycle to
execute, but if preceded immediately by a load, MAC, or MSAC instruction, the EMAC pipeline depth is
exposed and execution time is 3 cycles.
Table 3-19 lists EMAC execution times.
(Ay)+ 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)
-(Ay) 1(1/0) 21/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)
(d16,Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —
(d8,Ay,Xi*SF) 2(1/0) 3(1/1) 3(1/1) 3(1/1) — — —
(xxx).w 1(1/0) 2(1/1) 2(1/1) 2(1/1) — — —
(xxx).l 1(1/0) 2(1/1) 2(1/1) 2(1/1) — — —
(d16,PC) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —
(d8,PC,Xi*SF) 2(1/0) 3(1/1) 3(1/1) 3(1/1) — — —
# 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) — —
Table 3-12. Move Long Execution Times
Source
Destination
Rx (Ax) (Ax)+ –(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl
Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)
Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)
(Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)
(Ay)+ 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)
-(Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)
(d16,Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —
(d8,Ay,Xi*SF) 2(1/0) 3(1/1) 3(1/1) 3(1/1) — — —
(xxx).w 1(1/0) 2(1/1) 2(1/1) 2(1/1) — — —
(xxx).l 1(1/0) 2(1/1) 2(1/1) 2(1/1) — — —
(d16,PC) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —
(d8,PC,Xi*SF) 2(1/0) 3(1/1) 3(1/1) 3(1/1) — — —
# 1(0/0) 1(0/1) 1(0/1) 1(0/1) — — —
Table 3-11. Move Byte and Word Execution Times (Continued)
Source
Destination
Rx (Ax) (Ax)+ –(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl