Freescale Semiconductor MCF5480 - Manual (Page 402)

MCF548x Reference Manual, Rev. 3
15-30 Freescale Semiconductor
15.3.2.15 DSPI Pin Assignment Register (PAR_DSPI)
The PAR_DSPI register controls the functions of MCF548x DSPI pins. The PAR_DSPI register is
read/write.
Table 15-33. PAR_PCS0 Descriptions
Bits Name Description
7–6 PAR_CTS0 PSC0CTS pin assignment. Configures the PSC0CTS pin for one of its primary functions or general
purpose I/O.
0X PSC0CTS pin configured for general purpose I/O (PPSC1PSC03)
10 PSC0CTS pin configured for PSC0BCLK function
11 PSC0CTS pin configured for PSC0CTS function
5–4 PAR_RTS0 PSC0RTS pin assignment. Configures the PSC0RTS pin for one of its primary functions or general
purpose I/O.
0X PSC0RTS pin configured for general purpose I/O (PPSC1PSC02)
10 PSC0RTS pin configured for PSC0FSYNC function
11 PSC0RTS pin configured for PSC0RTS function
3 PAR_RXD0 PSC0RXD Pin Assignment. Configures the PSC0RXD pin for its primary function or general
purpose I/O.
0 PSC0RXD pin configured for general purpose I/O (PPSC1PSC01)
1 PSC0RXD pin configured for PSC0RXD function
2 PAR_TXD0 PSC0TXD Pin Assignment. Configures the PSC0TXD pin for its primary function or general
purpose I/O.
0 PSC0TXD pin configured for general purpose I/O (PPSC1PSC00)
1 PSC0TXD pin configured for PSC0TXD function
1–0 — Reserved, should be cleared.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 PAR_
CS5
PAR_CS3 PAR_CS2 PAR_CS0 PAR_SCK PAR_SIN PAR_SOUT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0xA50 (PAR_DSPI)
Figure 15-32. DSPI Pin Assignment Register (PAR_DSPI)
Table 15-34. PAR_DSPI Descriptions
Bits Name Description
15–13 — Reserved, should be cleared.
12 PAR_CS5 DSPICS5/PCSS pin assignment. Configures the DSPICS5/PCSS pin for its primary function or
general purpose I/O.
0 DSPICS5/PCSS pin configured for general purpose I/O (PDSPI6)
1 DSPICS5/PCSS pin configured for DSPICS5/PCSS function