9 tx fifo data register (pcitfdr), 10 tx fifo status register (pcitfsr) – Freescale Semiconductor MCF5480 User Manual
Page 515
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
19-31
19.3.3.1.9
Tx FIFO Data Register (PCITFDR)
+
19.3.3.1.10 Tx FIFO Status Register (PCITFSR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
FIFO_Data_Word
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
FIFO_Data_Word
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8440
Figure 19-28. Tx FIFO Data Register (PCITFDR)
Table 19-27. PCITFDR Field Descriptions
Bits
Name
Description
31–0
FIFO_Data
_Word
This is the data port to the FIFO. Reading from this location will “pop” data from the FIFO, writing
data will “push” data into the FIFO. During normal operation the multichannel DMA controller will
be pushing data here. The PCI controller will pop data for transmission from a dedicated peripheral
port, so the user program should not be reading here.
Note: Only full 32-bit accesses are allowed. If all FIFO byte enables are not asserted when
accessing this location, FIFO data will be corrupted.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
IP
TXW
0
0
0
0
0
0
FAE
RXW
UF
OF
FR
Full
Alarm Empt
y
W rwc
1
rwc
1
rwc
1
rwc
1
rwc
1
rwc
1
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8444
1
Bits 31, 30 and 23-20 are read-write-clear (rwc).
—Hardware can set rwc bits, but cannot clear them.
—Software can clear rwc bits that are currently set by writing a 1 to the bit location. Writing a 1 to a rwc bit that is
currently a 0 or writing a 0 to any rwc bit has no effect.
Figure 19-29. Tx FIFO Status Register (PCITFSR)