Freescale Semiconductor MCF5480 - Manual (Page 68)

MCF548x Reference Manual, Rev. 3
1-10 Freescale Semiconductor
• DMA support
1.4.6.7 Controller Area Network (CAN)
The FlexCAN modules are communication controllers implementing the CAN protocol. The CAN
protocol can be used as an industrial control serial data bus, meeting the specific requirements of real-time
processing and reliable operation in a harsh EMI environment, while maintaining cost-effectiveness. Each
of the two CAN controllers on the MCF548x family products contains sixteen message buffers. The CAN
controllers can be configured to either function as an interface with two separate CAN networks, or as a
single 32 message buffer CAN network.
1.4.7 DDR SDRAM Memory Controller
The DDR SDRAM memory controller is a glueless interface to DDR memories. The module uses a 32-bit
memory port and can address a maximum of 1 Gbyte of data with 16 64M x 8 (512-Mbit) devices, four
per chip select. The controller supplies two clock lines and respective inverted clock lines to help minimize
system complexity when using DDR. The module supports either DDR or SDR, but not both. This is due
to voltage differences between the memory technologies.
The supported memory clock rate is up to 133 MHz. At this memory clock rate, DDR memory can receive
data at an effective rate of up to 266 MHz.
• Support for up to 13 lines of row address, 11 lines of column address, two lines of bank address,
and up to four chip selects
• Memory bus width fixed at 32 bits
• Four chip selects support up to 1 GByte of SDRAM memory
• Support for page mode to maximize the data rate. Page mode remembers active pages for all four
chip selects
• Support for sleep mode and self refresh
• Cache line reads that can use critical word first. These reads can start in the center of a burst and
will wrap to the beginning. This allows the processor quicker access to a needed instruction.
All on-chip bus masters have access to DRAM. This includes PCI, the ColdFire V4e core, the
cryptography accelerator, and the DMA controller.
1.4.8 Peripheral Component Interconnect (PCI)
The PCI controller is a PCI V2.2-compliant bus controller and arbiter. The PCI bus is capable of 66-MHz
operation with a 32-bit address/data bus and support for five external masters.
The PCI module includes an inbound FIFO to increase performance when using an external bus master.
The bus can address all 4 Gbytes of PCI-addressable space.
The PCI bus is also multiplexed with the flexible local bus (FlexBus) address lines. If 32-bit non-muxed
local address and data is required, it can be obtained at the expense of utilizing the PCI bus.
When implemented, the PCI controller acts as the central resource, bus arbiter, and configuring master on
the PCI bus.
1.4.9 Flexible Local Bus (FlexBus)
The FlexBus module is intended to provide the user with basic functionality required to interface to
peripheral devices. The FlexBus interface is a multiplexed or non-multiplexed bus, with an operating