Freescale Semiconductor MCF5480 - Manual (Page 35)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor xxxv
Contents
Paragraph
Number
Title
Page
Number
28.3.2.1 I
2
C Address Register (I2ADR) ............................................................................. 28-3
28.3.2.2 I
2
C Frequency Divider Register (I2FDR) ............................................................ 28-4
28.3.2.3 I
2
C Control Register (I2CR) ................................................................................. 28-5
28.3.2.4 I
2
C Status Register (I2SR) .................................................................................... 28-5
28.3.2.5 I
2
C Data I/O Register (I2DR) ............................................................................... 28-7
28.3.2.6 I
2
C Interrupt Control Register (I2ICR) ................................................................ 28-7
28.4 Functional Description .................................................................................................. 28-8
28.4.1 START Signal ........................................................................................................... 28-9
28.4.2 Slave Address Transmission ..................................................................................... 28-9
28.4.3 STOP Signal ............................................................................................................. 28-9
28.4.4 Data Transfer ............................................................................................................ 28-9
28.4.5 Acknowledge .......................................................................................................... 28-10
28.4.6 Repeated Start ......................................................................................................... 28-11
28.4.7 Clock Synchronization and Arbitration .................................................................. 28-11
28.4.8 Handshaking and Clock Stretching ......................................................................... 28-12
28.5 Initialization Sequence ................................................................................................ 28-12
28.5.1 Transfer Initiation and Interrupt ............................................................................. 28-13
28.5.2 Post-Transfer Software Response ........................................................................... 28-14
28.5.3 Generation of STOP ................................................................................................ 28-15
28.5.4 Generation of Repeated START ............................................................................. 28-16
28.5.5 Slave Mode ............................................................................................................. 28-16
28.5.6 Arbitration Lost ....................................................................................................... 28-18
28.5.7 Flow Control ........................................................................................................... 28-18
Chapter 29
USB 2.0 Device Controller
29.1 Introduction ................................................................................................................... 29-1
29.1.1 Overview ................................................................................................................... 29-1
29.1.2 Features ..................................................................................................................... 29-1
29.1.3 Block Diagram .......................................................................................................... 29-2
29.1.3.1 Controller and Synchronization ............................................................................ 29-2
29.1.3.2 Descriptor RAM ................................................................................................... 29-2
29.1.3.3 FIFO Controller .................................................................................................... 29-3
29.1.3.4 FIFO RAM Manager ............................................................................................ 29-3
29.1.3.5 Integrated USB 2.0 Transceiver ........................................................................... 29-3
29.2 Memory Map/Register Definition ................................................................................ 29-4
29.2.1 USB Memory Map .................................................................................................... 29-4
29.2.2 USB Request, Control, and Status Registers ............................................................ 29-9
29.2.2.1 USB Status Register (USBSR) ............................................................................. 29-9
29.2.2.2 USB Control Register (USBCR) ........................................................................ 29-10