Freescale Semiconductor MCF5480 - Manual (Page 330)

MCF548x Reference Manual, Rev. 3
10-8 Freescale Semiconductor
10.3.2.3 Watchdog Functions
10.3.2.3.1 Timer Functions
There are three watchdog timers: address tenure time out, data tenure time out, and bus activity time out.
Each has a programmable timer count and can be disabled. A timer time-out will set a status bit and trigger
an interrupt if that interrupt is enabled.
• The address tenure watchdog is a 32-bit timer. If an acknowledge is not detected by the
programmed number of clocks after bus grant is accepted, the address watchdog timer will expire
and the arbiter will issue an acknowledge. The related data tenure will be terminated with a transfer
error acknowledge. The arbiter will set the Address Tenure Time-out Status bit in the arbiter status
register and issue an interrupt if that interrupt is enabled.
The upper 28 bits of address tenure time-out are programmed via the address tenure time-out
register. The lower 4 bits are always 0xF.
• The data tenure watchdog is a 32-bit timer. If a data tenure is not terminated, the data watchdog
timer will expire and the arbiter will issue a transfer error acknowledge. The arbiter will set the
Data Tenure Time-out Status bit in the arbiter status register and issue an interrupt if that interrupt
is enabled.
Address Time-out (32 bits) = {address tenure time-out register (28bits), 0xF}
Data Time-out (32 bits) = {data tenure time-out register (28 bits), 0xF}
• The bus activity watchdog is a 32-bit timer. If no bus activity is detected by the programmed
number of clocks, the bus activity watchdog timer will expire and the arbiter will set the Bus
Activity Time-out Status bit in the arbiter status register and issue an interrupt if that interrupt is
enabled.
NOTE
Enabling the data time-out will also enable the address time-out. It is
recommended that the data watchdog timer should always be programmed
to a value that is larger than the address watchdog timer. This prevents the
XL bus arbiter from generating a transfer error acknowledge due to
expiration of the data watchdog timer while the address tenure has not
completed.
10.3.3 XLB Arbiter Register Descriptions
The XLB Arbiter registers and their locations are defined in Table 10-4 .
Table 10-4. XL Bus Arbiter Memory Map
MBAR
Offset
Name Byte0 Byte1 Byte2 Byte3 Access
0x240 Arbiter Configuration Register XARB_CFG R/W
0x244 Arbiter Version Register XARB_VER R
0x248 Arbiter Status Register XARB_SR R/W
0x24C Arbiter Interrupt Mask Register XARB_IMR R/W
0x250 Arbiter Address Capture XARB_ADRCAP R/W
0x254 Arbiter Signal Capture XARB_SIGCAP R/W