1 rx packet size register (pcirpsr), 2 rx start address register (pcirsar) – Freescale Semiconductor MCF5480 User Manual
Page 520
MCF548x Reference Manual, Rev. 3
19-36
Freescale Semiconductor
19.3.3.2.1
Rx Packet Size Register (PCIRPSR)
19.3.3.2.2
Rx Start Address Register (PCIRSAR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
Packet_Size[15:2]
Packet_Size
[1:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8480
Figure 19-34. Rx Packet Size Register (PCIRPSR)
Table 19-33. PCIRPSR Field Descriptions
Bits
Name
Description
31–18
Packet_Size Packet_Size [15:2]. The Packet_Size field indicates the number of bytes for the receive controller
to read over PCI. Only bits [15:2] are writable. Only 32-bit data transfers to the FIFO are allowed.
Writing to this register also completes a Restart Sequence as long as the Master Enable bit,
PCIRER[ME], is high and Reset Controller bit, PCIRER[RC], is low.
17-16
Packet_Size [1:0] The two low bits are hardwired low.
15–0
—
Reserved, should be cleared. No Bus Error is generated.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
Start_Add
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
Start_Add
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8484
Figure 19-35. Rx Start Address Register (PCIRSAR)