Freescale Semiconductor MCF5480 - Manual (Page 393)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 15-21
15.3.2.5 Port x Pin Assignment Registers (PAR_x)
The PAR_x registers select the signal function that will be driven on the physical pin.
15.3.2.5.1 FlexBus Control Pin Assignment Register (PAR_FBCTL)
The FlexBus control pin assignment (PAR_FBCTL) register controls the function of the FlexBus control
signal pins. The PAR_FBCTL register is read/write.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W CLRFB5 CLRFB4 CLRFB3 CLRFB2 CLRFB1
Reset 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0xA31 (PCLRR_FBCS)
Figure 15-21. 5-Bit FlexBus Clear Output Data Register
Table 15-23. 5-Bit PCLRR_FBCS Field Descriptions
Bits Name Description
7–6 — Reserved, should be cleared
5–1 CLRFBn PCLRR_FBCS clear output data register
0 Corresponding PODR_FBCS bit is cleared
1 No effect
0 — Reserved, should be cleared
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 PAR_
BWE3
0 PAR_
BWE2
0 PAR_
BWE1
0 PAR_
BWE0
0 PAR_
OE
PAR_RWB 0 PAR_
TA
PAR_ALE
W
Reset 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1
Reg
Addr
MBAR + 0xA40 (PAR_FBCTL)
Figure 15-22. FlexBus Control Pin Assignment Register (PAR_FBCTL)
Table 15-24. PAR_FBCTL Field Descriptions
Bits Name Description
15 — Reserved, should be cleared.
14 PAR_BWE3 The PAR_BWE bit configures the BE3/BWE3 pin for its primary function or general purpose I/O.
0 BE3/BWE3 pin configured for general purpose I/O (PFBCTL7)
1 BE3/BWE3 pin configured for FlexBus BE3/BWE3 or TSIZ1 function.
The function chosen depends on the reset configuration.
13 — Reserved, should be cleared.