Freescale Semiconductor MCF5480 - Manual (Page 250)

MCF548x Reference Manual, Rev. 3
7-30 Freescale Semiconductor
In Table 7-10 the current state is modified.
7.13 Cache Initialization Code
The following example sets up the cache for FLASH or ROM space only.
move.l #0xA30C8100,D0 //enable cache, invalidate it,
//default mode is cache-inhibited imprecise
movec D0, CACR
move.l #0xFF00C000,D0 //cache FLASH space, enable,
//ignore FC2, cacheable, writethrough
movec D0,ACR0
Table 7-10. Data Cache Line State Transitions (Current State Modified)
Access Response
Read miss CD1 Push modified line to buffer;
read new line from memory and update cache;
supply data to processor;
write push buffer contents to memory;
go to valid state.
Read hit CD2 Supply data to processor;
stay in modified state.
Write miss
(copyback) CD3 Push modified line to buffer;
read new line from memory and update cache;
write push buffer contents to memory;
stay in modified state.
Write miss
(write-through) WD3 Write data to memory;
stay in modified state.
Cache mode changed for the region corresponding to this line. To avoid this state, execute
a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes.
Write hit
(copyback) CD4 Write data to cache;
stay in modified state.
Write hit
(write-through) WD4 Write data to memory and to cache;
go to valid state.
Cache mode changed for the region corresponding to this line. To avoid this state, execute
a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes.
Cache invalidate CD5 No action (modified data lost);
go to invalid state.
Cache push CD6 Push modified line to memory;
go to invalid state.
Cache push CD7 Push modified line to memory;
go to valid state.