12 tx fifo alarm register (pcitfar) – Freescale Semiconductor MCF5480 User Manual
Page 517
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
19-33
19.3.3.1.12 Tx FIFO Alarm Register (PCITFAR)
Table 19-29. PCITFCR Field Descriptions
Bits
Name
Description
31–30
—
Reserved, should be cleared.
29
WFR
Write frame. When this bit is set, the FIFO controller assumes next data transmitted is End of
Frame (EOF).
Note: This module does not support Framing. This bit should remain low.
28-27
—
Reserved, should be cleared.
26–24
GR[2:0]
Granularity. Control high “watermark” point at which FIFO negates Alarm condition (i.e., request
for data). It represents the number of free bytes times 4.
A granularity setting of zero should be avoided because it means the Alarm bit (and the
Requestor signal) will not negate until the FIFO is completely full. The multichannel DMA module
may perform up to 2 additional data writes after the negation of a Requestor due to its internal
pipelining.
23
IP_MASK
Illegal pointer mask. When this bit is set, the FIFO controller masks the Status register’s IP bit
from generating an error.
22
FAE_MASK Frame accept error mask. When this bit is set, the FIFO controller masks the Status Register’s
FAE bit from generating an error.
21
RXW_MASK Receive wait condition mask. When this bit is set, the FIFO controller masks the Status
Register’s RXW bit from generating an error. (To help with backward compatibility, this bit is
asserted at reset.)
20
UF_MASK
Underflow mask. When this bit is set, the FIFO controller masks the Status Register’s UF bit from
generating an error.
19
OF_MASK
Overflow mask. When this bit is set, the FIFO controller masks the Status Register’s OF bit from
generating an error.
18
TXW_MASK Transmit wait condition mask. When this bit is set, the FIFO controller masks the Status
Register’s TXW bit from generating an error. (To help with backward compatibility, this bit is
asserted at reset.)
17–0
—
Reserved, should be cleared.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
Alarm
Alarm
W
Reset
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Reg
Addr
MBAR + 0x844C
Figure 19-31. Tx FIFO Alarm Register (PCITFAR)