Freescale Semiconductor MCF5480 - Manual (Page 191)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 6-1
Chapter 6
Floating-Point Unit (FPU)
6.1 Introduction
This chapter describes instructions implemented in the floating-point unit (FPU) designed for use with the
ColdFire family of microprocessors. The FPU conforms to the American National Standards Institute
(ANSI)/Institute of Electrical and Electronics Engineers (IEEE) Standard for Binary Floating-Point
Arithmetic (ANSI/IEEE Standard 754).
The hardware unit is optimized for real-time execution with exceptions disabled and default results
provided for specific operations, operands, and number types. The FPU does not support all IEEE-754
number types and operations in hardware. Exceptions can be enabled to support these cases in software.
6.1.1 Overview
The FPU operates on 64-bit, double-precision, floating-point data and supports single-precision and signed
integer input operands. The FPU programming model is like that in the MC68060 microprocessor. The
FPU is intended to accelerate the performance of certain classes of embedded applications, especially
those requiring high-speed floating-point arithmetic computations. See Section 6.7.3, “Key Differences
between ColdFire and M68000 FPU Programming Models .”
The FPU appears as another execute engine at the bottom stages of the operand execution pipeline (OEP),
using operands from a dual-ported register file.
Setting bit 4 in the cache control register (CACR[DF]) disables the FPU. If CACR[DF] is cleared, all FPU
instructions are issued and executed, otherwise the processor responds with an unimplemented line-F
instruction exception (vector 11).
Operating systems often assume user applications are integer-only (to minimize the time required by save
context) by setting CACR[DF] at process initiation. If the application includes floating-point instructions,
the attempted execution of the first FP instruction generates the unimplemented line-F exception, which
signals the kernel that the FPU registers must be included in the context for the application. The application
then continues execution with CACR[DF] cleared to enable FPU execution.
6.1.1.1 Notational Conventions
Table 6-1 defines notational conventions used in this chapter.
Table 6-1. Notational Conventions
Symbol Description
Single- and Double-Precision Operand Operations
+
Arithmetic addition or postincrement indicator
−
Arithmetic subtraction or predecrement indicator
×
Arithmetic multiplication
÷
Arithmetic division or conjunction symbol
∼
Invert, operand is logically complemented. An overbar, , is also used for this operation.