Freescale Semiconductor MCF5480 - Manual (Page 131)

Instruction Execution Timing
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 3-27
3.7 Instruction Execution Timing
The timing data in this section assumes the following:
• Execution times for individual instructions make no assumptions concerning the OEP’s ability to
dispatch multiple instructions in one machine cycle. For sequences where instruction pairs are
issued, the execution time of the first instruction defines the execution time of pair; the second
instruction effectively executes in zero cycles.
• The OEP is loaded with the opword and all required extension words at the beginning of each
instruction execution. This implies that the OEP spends no time waiting for the IFP to supply
opwords or extension words.
• The OEP experiences no sequence-related pipeline stalls. For the V4, the most common example
of this type of stall occurs when a register is modified in the EX engine and a subsequent instruction
generates an address that uses the previously modified register. The second instruction stalls in the
OEP until the previous instruction updates the register. For example:
muls.l #,d0
move.l (a0,d0.l*4),d1
move.l waits 3 cycles for the muls.l to update d0. If consecutive instructions update a register and
use that register as a base of index value with a scale factor of 1 (Xi.l*1) in an address calculation,
a 2-cycle pipeline stall occurs. If the destination register is used as an index register with any other
scale factor (Xi.l*2, Xi.l*4), a 3-cycle stall occurs.
NOTE
Address register results from postincrement and predecrement modes are
available to subsequent instructions without stalls.
Table 3-9. Supervisor-Mode Instruction Set Summary
Instruction Operand Syntax Operand Size Operation
CPUSHL ic,(Ax)
dc,(Ax)
bc,(Ax)
none If data is valid and modified, push cache line; invalidate line
if programmed in CACR (synchronizes pipeline)
FRESTORE y none FPU State Frame
→ Internal FPU State
FSAVE x none Internal FPU State
→ FPU State Frame
HALT none none Halt processor core
INTOUCH Ay none Instruction fetch touch at (Ay)
MOVE from SR SR,Dx W SR
→ Destination
MOVE from USP USP,Dx L USP
→ Destination
MOVE to SR y,SR W Source
→ SR; Dy or # source only
MOVE to USP Ay,USP L Source
→ USP
MOVEC Ry,Rc L Ry
→ Rc
RTE none none 2 (SP)
→ SR; 4 (SP) → PC; SP + 8 →SP
Adjust stack according to format
STOP # none Immediate Data
→ SR; STOP
WDEBUG y L Addressed Debug WDMREG Command Executed