Freescale Semiconductor MCF5480 - Manual (Page 110)

MCF548x Reference Manual, Rev. 3
3-6 Freescale Semiconductor
The hardware unit is optimized for real-time execution with exceptions disabled and default results
provided for specific operations, operands, and number types. The FPU does not support all IEEE-754
number types and operations in hardware. Exceptions can be enabled to support these cases in software.
3.2.1.2.5 Hardware Divide Unit
The hardware divide unit performs the following integer division operations:
• 32-bit operand/16-bit operand producing a 16-bit quotient and a 16-bit remainder
• 32-bit operand/32-bit operand producing a 32-bit quotient
• 32-bit operand/32-bit operand producing a 32-bit remainder
3.2.1.3 Harvard Memory Architecture
A Harvard memory architecture supports the increased bandwidth requirements of the CF4e processor
pipelines by providing separate configuration, access control, and protection resources for data (operand)
and instruction memory. The CF4e has separate instruction and data buses to processor-local memories,
eliminating conflicts between instruction fetches and operand accesses.
3.2.2 Debug Module Enhancements
The ColdFire processor core debug interface supports system integration in conjunction with low-cost
development tools. Real-time trace and debug information can be accessed through a standard interface,
which allows the processor and system to be debugged at full speed without costly in-circuit emulators.
The CF4e debug unit is a compatible upgrade to MCF52xx and MCF53xx debug modules with added
support for the CF4e MMU module.
The Version 2 ColdFire core implemented the original debug architecture, now called Revision A. Based
on feedback from customers and third-party developers, enhancements have been added to succeeding
generations of ColdFire cores. For Revision A, CSR[HRL] is 0. See Section 8.4.2, “Configuration/Status
Register (CSR).”
The Version 3 core implements Revision B of the debug architecture, offering more flexibility for
configuring the hardware breakpoint trigger registers and removing the restrictions involving concurrent
BDM processing while hardware breakpoint registers are active. For Revision B, CSR[HRL] is 1.
Revision C of the debug architecture more than doubles the on-chip breakpoint registers and provides an
ability to interrupt debug service routines. For Revision C, CSR[HRL] is 2.
Differences between Revision B and C are summarized as follows:
• Debug Revision B has separate PST[3:0] and DDATA[3:0] signals.
• Debug Revision C adds breakpoint registers and supports normal interrupt request service during
debug. It combines debug signals into PSTDDATA[7:0].
The addition of the memory management unit (MMU) to the baseline architecture requires corresponding
enhancements to the ColdFire debug functionality, resulting in Revision D. For Revision D, the revision
level bit, CSR[HRL], is 3.
With software support, the MMU can provide a demand-paged, virtual address environment. To support
debugging in this virtual environment, the debug enhancements are primarily related to the expansion of
the virtual address to include the 8-bit address space identifier (ASID). Conceptually, the virtual address
is expanded to a 40-bit value: the 8-bit ASID plus the 32-bit address.
The expansion of the virtual address affects the following two major debug functions: