Freescale Semiconductor MCF5480 - Manual (Page 722)

MCF548x Reference Manual, Rev. 3
24-2 Freescale Semiconductor
24.1.2 Overview
The DMA controller processes microcode tasks that are stored in memory. A task is a sequence of
instructions, referred to as descriptors, that specifies a series of data movements or manipulations. The
DMA controller steps through the descriptors and executes the specified function in a similar fashion to a
CPU executing a program.
24.1.2.1 Master DMA Engine (MDE)
The MDE is the main interpreter for the multichannel DMA. It parses descriptors and sets up the other
blocks to perform the actual data movement and manipulation. It also manages context switches. For more
MDE information see Section 24.5, “Programming Model .”
24.1.2.2 Address and Data Sequencer (ADS)
The ADS is the engine that pumps data through the multichannel DMA. Based on configuration bits set
by the MDE (derived from the application program), the ADS will fetch operands, route them through
execution units, store results as appropriate, and evaluate termination conditions.
24.1.2.3 Priority-Task Decoder (PTD)
The PTD manages prioritization of initiators and maintains the mapping from initiator to task number. The
user has complete control of initiator priority. The PTD also maintains error status and control.
24.1.2.4 Logic Unit with Redundancy Check (LURC)
The LURC can perform several arithmetic and logical operations including addition, subtraction, logical
shifts, binary operations, and checksum calculations. The LURC can perform as many as five boolean
operations on up to four operands and provides an efficient mechanism for performing endian conversions.
The checksum unit can compute the following CRC polynomials: CRC-32, CRC-16, CRC-CCITT, and
the internet checksum.
24.1.2.5 Debug Unit
The Debug unit provides simple breakpoint functionality to halt tasks when they reach certain conditions.
24.1.3 Features
The DMA module has the following features:
• A programmatic, deterministic capability for managing bus resources while servicing many data
streams with individual latency and processing requirements.
• Single cycle access of peripheral and memory data.
• Support for up to 16 simultaneously enabled tasks (channels)
• Support for up to 32 separate DMA initiators at a time
• Simultaneous 32-bit reads and writes for many sources and targets
• Checksum generation
• Endian conversion
• Chaining/scatter-gather capability
• Support for packet-based I/O protocols