Table 21-8 describes the errstat fields – Freescale Semiconductor MCF5480 User Manual
Page 586
MCF548x Reference Manual, Rev. 3
21-16
Freescale Semiconductor
describes the ERRSTAT fields.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
BITERR
ACK
ERR
CRC
ERR
FRM
ERR
STF
ERR
TX
WRN
RX
WRN
IDLE TXRX
FLT
CONF
0
BOFF
INT
ERR
INT
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0xA020 (ERRSTAT0); 0xA820 (ERRSTAT1)
Figure 21-11. FlexCAN Error and Status Register (ERRSTAT)
Table 21-8. ERRSTAT Field Descriptions
Bits
Name
Description
31–16
—
Reserved, should be cleared.
15–14
BITERR
Transmit bit error. The BITERR[1:0] field is used to indicate when a transmit bit error occurs.
00 No transmit bit error
01 At least one bit sent as dominant was received as recessive
10 At least one bit sent as recessive was received as dominant
11 Reserved
Note: The transmit bit error field is not modified during the arbitration field or the ACK slot bit time
of a message, or by a transmitter that detects dominant bits while sending a passive error frame.
13
ACKERR
Acknowledge error. The ACKERR bit indicates whether an acknowledgment has been correctly
received for a transmitted message.
0 No ACK error was detected since the last read of this register.
1 An ACK error was detected since the last read of this register.
12
CRCERR
Cyclic redundancy check error. The CRCERR bit indicates whether or not the CRC of the last
transmitted or received message was valid.
0 No CRC error was detected since the last read of this register.
1 A CRC error was detected since the last read of this register.
11
FRMERR
Message format error. The FORMERR bit indicates whether or not the message format of the last
transmitted or received message was correct.
0 No format error was detected since the last read of this register.
1 A format error was detected since the last read of this register.
10
STFERR
Bit stuff error. The STUFFERR bit indicates whether or not the bit stuffing that occurred in the last
transmitted or received message was correct.
0 No bit stuffing error was detected since the last read of this register.
1 A bit stuffing error was detected since the last read of this register.
9
TXWRN
Transmit error status flag. The TXWARN status flag reflects the status of the FlexCAN transmit error
counter.
0 Transmit error counter
< 96
1 TXErrCounter
≥ 96