Freescale Semiconductor MCF5480 - Manual (Page 556)

MCF548x Reference Manual, Rev. 3
19-72 Freescale Semiconductor
19.5.2.1 Address Translation
19.5.2.1.1 Inbound Address Translation
The MCF548x-as-target occupies two memory target address windows on the PCI bus. The location is
determined by the values programmed to BAR0 and BAR1 of the PCI Type 00h configuration space.
These inbound memory window sizes are fixed to one 256-Kbyte window (BAR0) and one 1-Gbyte
window (BAR1).
PCI inbound address translation allows address translation to any space in MCF548x space (4 Gbytes of
address space). The target base address translation registers TBATR0 and TBATR1 specify the location of
the inbound memory window. These registers are described in Section 19.4.3, “Configuration Interface ”.
Address translation occurs for all enabled inbound transactions. If the enable bit of the target base address
translation registers is cleared, MCF548x aborts all PCI memory transactions to that base address window.
Note, the PCI configuring master can program BAR0 to overlap BAR1. The default address translation
value is TBATR1 in that case. It is not recommended to program overlapping BAR0 and BAR1 or
overlapping TBATR0 and TBATR1. An overlap of TBATRs can cause data write-over of BAR0 data.
The Initiator Window Base Address Registers are used to decode XL bus addresses for PCI bus
transactions. The base address and base address mask values define the upper byte of address to decode.
The XL bus address space in MCF548x dedicated to PCI transactions can be mapped to three 16-Mbyte
or larger address spaces in the MCF548x. Initiator Windows can be programmed to overlap, though not
recommended. Priority for the windows is 0, 1, 2. That is, initiator window 0 has priority over all others
and window 1 has priority over window 2.
In normal operation, software should not program either Target Address Window Translation Register to
address Initiator Window space. In that event, a MCF548x-as-Target transaction would propagate through
the MCF548x’s internal bus and request PCI bus access as the PCI Initiator. The PCI arbiter could see the
PCI bus as busy (target read transaction in progress) and only a time-out would free the PCI bus.