Freescale Semiconductor MCF5480 - Manual (Page 603)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 22-1
Chapter 22
Integrated Security Engine (SEC)
This chapter provides an overview of the MCF548x security encryption controller (SEC).
NOTE
Purchasing any of the MCF548x devices with security requires government
export control regulation.
22.1 Features
The SEC is designed to offload computationally intensive security functions, such as authentication bulk
encryption from the MCF548x core. It is optimized to process all the algorithms associated with IPSec,
SSL/TLS, iSCSI, and SRTP.
SEC features include the following:
• DEU—data encryption standard execution unit
— DES, 3DES
— Two key (K1, K2, K1) or three Key (K1, K2, K3)
— ECB and CBC modes for both DES and 3DES
• AESU—advanced encryption standard unit
— Implements the Rinjdael symmetric key cipher
— ECB, CBC, CCM, and counter modes
— 128, 192, 256 bit key lengths
• AFEU—ARC four execution unit
— Implements a stream cipher compatible with the RC4 algorithm
— 40- to 128-bit programmable key
• MDEU—message digest execution unit
— SHA with 160-bit or 256-bit message digest
— MD5 with 128-bit message digest
— HMAC with either algorithm
• RNG—one random number generator
• Master/slave logic, with DMA
— 32-bit address/32 -bit data
— Up to 133 MHz operation
• Two Crypto-channels, each supporting multi-command descriptor chains
— Static and/or dynamic assignment of crypto-execution units via an integrated controller
• Buffer size of 512 bytes for each execution unit, with flow control for large data sizes
22.2 ColdFire Security Architecture
The ability of the SEC to be a master on the internal XLB bus allows the security core to offload the data
movement bottleneck normally associated with slave-only cores.
The ColdFire core accesses the SEC primarily through data packet descriptors using system memory for
data storage. When an application requires cryptographic functions, it simply creates descriptors that