Freescale Semiconductor MCF5480 - Manual (Page 1027)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor Index-13
transfer burst (TBST) 2-17, 17-4
transfer size (TSIZn) 2-17, 17-4
transfer start (TS) 2-17, 17-4
FlexCAN
receive (CANRX0, CANRX1) 2-27
transmit (CANTX0, CANTX1) 2-27
general-purpose timers
inputs (TINn) 2-29
outputs (TOUTn) 2-29
GPIO 15-3–15-7
I
2
C
SCL 28-2
SDA 28-2
serial clock (SCL) 2-28
serial data (SDA) 2-28
interrupts
IRQn 2-21
JTAG
MTMOD0 23-2
test clock input (TCK) 23-3, 23-9
test data input/development serial input
(TDI/DSI) 23-3
test data output/development serial output
(TDO/DSO) 23-4
test mode select/breakpoint (TMS/BKPT) 23-3
test reset/development serial clock
(TRST/DSCLK) 23-4
PCI controller
addess/data (PCIADn) 2-20
clock (CLKIN) 19-3
command/byte enable (PCICXBEn) 2-20
device select (PCIDEVSEL) 2-20
external bus grant (PCIBGn) 2-21
external bus grant/request output
(PCIBG0/PCIREQOUT) 2-21
external bus request (PCIBRn) 2-21
external request/grant input
(PCIBR0/PCIGNTIN) 2-21
frame (PCIFRAME) 19-3
frame (PCIFRM) 2-20
initialization device select (PCIIDSEL) 2-20
initiator ready (PCIIRDY) 2-20
parity (PCIPAR) 2-20
parity error (PCIERR) 19-3
parity error (PCIPERR) 2-20
reset (PCIRESET) 2-21
stop (PCISTOP) 2-21, 19-3
system error (PCISERR) 2-21
target ready (PCITRDY) 2-21
power and reference
EVDD 2-31
IVDD 2-31
PLLVDD 2-31
PLLVSS 2-31
SDVDD 2-31
USB_OSCAVDD 2-31
USB_OSCVDD 2-31
USB_PHYVDD 2-31
USB_PLLVDD 2-31
USBVDD 2-31
VSS 2-31
PSC
clear-to-send (PSCnCTS/PSCBCLK) 2-28
PSCnCTS/PSCBCLK 26-2
PSCnRTS/PSCFSYNC 26-2
PSCnRXD 26-2
PSCnTXD 26-3
receive serial data input (PSCnRXD) 2-28
request-to-send (PSCnRTS/PSCFSYNC) 2-28
transmit serial data output (PSCnTXD) 2-28
reset configuration
32-bit FlexBus (FBMODE) 2-23
auto acknowledge (AACONFIG) 2-24
byte enable (BECONFIG) 2-23
CLKCONFIGn 2-22
FlexBus size (FBSIZE) 2-23
port size (PSCONFIG) 2-24
reset controller
reset in (RSTI) 2-22
reset out (RSTO) 2-22
SDRAM
clock enable 18-4
column address strobe 18-3
row address strobe 18-3
write enable 18-3
SDRAM controller
address bus (SDADDRn) 2-18, 18-2
bank address (SDBAn) 18-2
bank addresses (SDBAn) 2-19
chip select (SDCSn) 2-19
chip selects (SDCSn) 18-3
clock (SDCLCKn) 18-3
clock (SDCLKn) 2-19
clock enable (SDCKE) 2-19, 18-4
column address strobe (CAS) 2-19, 18-3
data bus (SDDATAn) 2-18, 18-2
data strobe (SDDQSn) 2-19
data strobe (SDDQSn) 18-3
data strobe (SDRDQS) 18-4
inverted clock (SDCLKn) 2-19, 18-3
memory supply (SDVDD) 18-4
reference voltage (VREF) 2-20, 18-4
row address strobe (RAS) 2-19, 18-3
SDR data strobe (SDRDQS) 2-19