Freescale Semiconductor MCF5480 - Manual (Page 8)

MCF548x Reference Manual, Rev. 3
viii Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
2.2.11 I
2
C I/O Signals .......................................................................................................... 2-27
2.2.11.1 Serial Clock (SCL) ............................................................................................... 2-28
2.2.11.2 Serial Data (SDA) ................................................................................................. 2-28
2.2.12 PSC Module Signals ................................................................................................. 2-28
2.2.12.1 Transmit Serial Data Output (PSC0TXD, PSC1TXD, PSC2TXD, PSC3TXD) .. 2-28
2.2.12.2 Receive Serial Data Input (PSC0RXD, PSC1RXD, PSC2RXD, PSC3RXD) ..... 2-28
2.2.12.3 Clear-to-Send (PSCnCTS/PSCBCLK) ................................................................. 2-28
2.2.12.4 Request-to-Send (PSCnRTS/PSCFSYNC) ........................................................... 2-28
2.2.13 DMA Controller Module Signals ............................................................................. 2-28
2.2.13.1 DMA Request (DREQ[1:0]) ................................................................................. 2-28
2.2.13.2 DMA Acknowledge (DACK[1:0]) ....................................................................... 2-28
2.2.14 Timer Module Signals .............................................................................................. 2-29
2.2.14.1 Timer Inputs (TIN[3:0]) ....................................................................................... 2-29
2.2.14.2 Timer Outputs (TOUT[3:0]) ................................................................................. 2-29
2.2.15 Debug Support Signals ............................................................................................. 2-29
2.2.15.1 Processor Clock Output (PSTCLK) ...................................................................... 2-29
2.2.15.2 Processor Status Debug Data (PSTDDATA[7:0]) ............................................... 2-29
2.2.15.3 Development Serial Clock/Test Reset (DSCLK/TRST) ...................................... 2-29
2.2.15.4 Breakpoint/Test Mode Select (BKPT/TMS) ........................................................ 2-30
2.2.15.5 Development Serial Input/Test Data Input (DSI/TDI) ......................................... 2-30
2.2.15.6 Development Serial Output/Test Data Output (DSO/TDO) ................................. 2-30
2.2.15.7 Test Clock (TCK) ................................................................................................. 2-30
2.2.16 Test Signals ............................................................................................................... 2-30
2.2.16.1 Test Mode (MTMOD[3:0]) .................................................................................. 2-30
2.2.17 Power and Reference Pins ........................................................................................ 2-31
2.2.17.1 Positive Pad Supply (EVDD) ............................................................................... 2-31
2.2.17.2 Positive Core Supply (IVDD) ............................................................................... 2-31
2.2.17.3 Ground (VSS) ....................................................................................................... 2-31
2.2.17.4 USB Power (USBVDD) ....................................................................................... 2-31
2.2.17.5 USB Oscillator Power (USB_OSCVDD) ............................................................. 2-31
2.2.17.6 USB PHY Power (USB_PHYVDD) .................................................................... 2-31
2.2.17.7 USB Oscillator Analog Power (USB_OSCAVDD) ............................................. 2-31
2.2.17.8 USB PLL Analog Power (USB_PLLVDD) ......................................................... 2-31
2.2.17.9 SDRAM Memory Supply (SDVDD) .................................................................... 2-31
2.2.17.10 PLL Analog Power (PLLVDD) ............................................................................ 2-31
2.2.17.11 PLL Analog Ground (PLLVSS) ........................................................................... 2-31