Freescale Semiconductor MCF5480 User Manual
Page 268
MCF548x Reference Manual, Rev. 3
8-18
Freescale Semiconductor
taken under the defined conditions. Breakpoint logic may be configured as one- or two-level triggers.
TDR[31–16] or XTDR[31–16] define second-level triggers, and bits 15–0 define first-level triggers.
TDR is accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and
through the BDM port using the
WDMREG
command.
NOTE
The debug module has no hardware interlocks, so to prevent spurious
breakpoint triggers while the breakpoint registers are being loaded, disable
TDR and XTDR (by clearing TDR[29,13] and XTDR[29,13]) before
defining triggers.
A write to TDR clears the CSR trigger status bits, CSR[BSTAT].
When cleared, the data enable bits (EDxx) for both the second level and first level triggers disable data
breakpoints. When set, these bits enable the corresponding data breakpoint condition based on the size and
placement on the processor’s local data bus.
The address breakpoint for each trigger is enabled by setting the address enable bits (EAx); clearing all
three bits disables the corresponding breakpoint.
describes TDR fields.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Second Level Triggers
R
TRC
EBL
2
EDLW
2
EDWL
2
EDWU
2
EDLL
2
EDLM
2
EDUM
2
EDUU
2
DI
2
EAI
2
EAR
2
EAL
2
EPC
2
PCI
2
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
First Level Triggers
R
0
0
EBL
1
EDLW
1
EDWL
1
EDWU
1
EDLL
1
EDLM
1
EDUM
1
EDUU
1
DI
1
EAI
1
EAR
1
EAL
1
EPC
1
PCI
1
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
CPU + 0x07
Figure 8-10. Trigger Definition Register (TDR)
Table 8-12. TDR Field Descriptions
Bits
Name
Description
31–30
TRC
Trigger response control. Determines how the processor responds to a completed trigger
condition. The trigger response is always displayed on PSTDDATA.
00 Display on PSTDDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
29
EBL2
Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] or XTDR[EBL]
enables a breakpoint trigger. If both TDL[EBL] and XTDL[EBL] are cleared, all breakpoints are
disabled.