Freescale Semiconductor MCF5480 - Manual (Page 167)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 5-1
Chapter 5
Memory Management Unit (MMU)
This chapter describes the ColdFire virtual memory management unit (MMU), which provides
virtual-to-physical address translation and memory access control. The MMU consists of memory-mapped
control, status, and fault registers that provide access to translation-lookaside buffers (TLBs). Software can
control address translation and access attributes of a virtual address by configuring MMU control registers
and loading TLBs. With software support, the MMU provides demand-paged, virtual addressing.
5.1 Features
The MMU has the following features:
• MMU memory-mapped control, status, and fault registers
— Support a flexible, software-defined virtual environment
— Provide control and maintenance of TLBs
— Provide fault status and recovery information functions
• Separate, 32-entry, fully associative instruction and data TLBs (Harvard TLBs)
— Resides in the controller
— Operates in parallel with the memories
— Suffers no performance penalty on TLB hits
— Supports 1-, 4-, and 8-Kbyte and 1-Mbyte page sizes concurrently
— Contains register-based TLB entries
• Core extensions:
— User stack pointer
— All access error exceptions are precise and recoverable
• Harvard TLB provides 97% of baseline performance on large embedded applications using
equivalent V4 without MMU support as a baseline.
5.2 Virtual Memory Management Architecture
The ColdFire memory management architecture provides a demand-paged, virtual-address environment
with hardware address translation acceleration. It supports supervisor/user, read, write, and execute
permission checking on a per-memory request basis.
The architecture defines the MMU TLB, associated control logic, TLB hit/miss logic, address translation
based on the TLB contents, and access faults due to TLB misses and access violations. It intentionally
leaves some virtual environment details undefined to maximize the software-defined flexibility. These
include the exact structure of the memory-resident pointer descriptor/page descriptor tables, the base
registers for these tables, the exact information stored in the tables, the methodology (if any) for
maintenance of access, and written information on a per-page basis.
5.2.1 MMU Architecture Features
To add optional virtual addressing support, demand-page support, permission checking, and hardware
address translation acceleration to the ColdFire architecture, the MMU architecture features the following:
• Addresses from the core to the MMU are treated as physical or virtual addresses.