Freescale Semiconductor MCF5480 - Manual (Page 336)

MCF548x Reference Manual, Rev. 3
10-14 Freescale Semiconductor
10.3.3.7 Arbiter Address Tenure Time Out Register (XARB_ADRTO)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 TSIZ[0:2] — TBST TT[0:4]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0x0254
Figure 10-10. Arbiter Bus Signal Capture Register (XARB_SIGCAP)
Table 10-10. XARB_SIGCAP Field Descriptions
Bits Name Description
31–10 — Reserved, should be cleared.
9–7 TSIZ[0:2] TSIZ[0:2]
6 — Reserved, should be cleared
5 TBST TBST
4–0 TT TT[0:4]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 0 ADRTO
W
Reset 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADRTO
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reg
Addr
MBAR + 0x0258
Figure 10-11. Arbiter Address Tenure Time Out Register (XARB_ADRTO)