Freescale Semiconductor MCF5480 - Manual (Page 100)

MCF548x Reference Manual, Rev. 3
2-30 Freescale Semiconductor
2.2.15.4 Breakpoint/Test Mode Select (BKPT/TMS)
If MTMOD0 is low, BKPT is selected. BKPT signals a hardware breakpoint to the processor in debug
mode.
If MTMOD0 is high, TMS is selected. The TMS input provides information to determine the JTAG test
operation mode. The state of TMS and the internal 16-state JTAG controller state machine at the rising
edge of TCK determine whether the JTAG controller holds its current state or advances to the next state.
This directly controls whether JTAG data or instruction operations occur. TMS has an internal pull-up
resistor so that if it is not driven low, it defaults to a logic level of 1. But if TMS is not used, it should be
tied to V
DD
.
2.2.15.5 Development Serial Input/Test Data Input (DSI/TDI)
If MTMOD0 is low, DSI is selected. DSI provides the single-bit communication for debug module
commands.
If MTMOD0 is high, TDI is selected. TDI provides the serial data port for loading the various JTAG
boundary scan, bypass, and instruction registers. Shifting in data depends on the state of the JTAG
controller state machine and the instruction in the instruction register. Shifts occur on the TCK rising edge.
TDI has an internal pull-up resistor, so when not driven low it defaults to high. But if TDI is not used, it
should be tied to EVDD.
2.2.15.6 Development Serial Output/Test Data Output (DSO/TDO)
If MTMOD0 is low, DSO is selected. DSO provides single-bit communication for debug module
responses.
If MTMOD0 is high, TDO is selected. The TDO output provides the serial data port for outputting data
from JTAG logic. Shifting out data depends on the JTAG controller state machine and the instruction in
the instruction register. Data shifting occurs on the falling edge of TCK. When TDO is not outputting test
data, it is three-stated. TDO can be three-stated to allow bused or parallel connections to other devices
having a JTAG port.
2.2.15.7 Test Clock (TCK)
TCK is the dedicated JTAG test logic clock independent of the MCF548x processor clock. Various JTAG
operations occur on the rising or falling edge of TCK. Holding TCK high or low for an indefinite period
does not cause JTAG test logic to lose state information. If TCK is not used, it must be tied to ground.
2.2.16 Test Signals
2.2.16.1 Test Mode (MTMOD[3:0])
The test mode signals choose between multiplexed debug module and JTAG signals. If MTMOD0 is low,
the part is in normal and background debug mode (BDM); if it is high, it is in normal and JTAG mode. All
other MTMOD values are reserved; MTMOD[3:1] should be tied to ground and MTMOD[3:0] should not
be changed while RSTI is negated